U. Glaeser

2
σ
where is the variance of Gamma distribution function. The parameter can be used to account
for defect clustering.
By varying this parameter, the model covers the entire range of yield predictions.
The larger variance means more clustering of defects. If the parameter is equal to 1, this yield model
2
reduces to the Price formula (exponential weighting). On the contrary, for σ = 0, it becomes the Poisson
formula (no clustering). The value of the clustering parameter must be experimentally determined. The
smaller values reflect higher yield and occur with maturity of technology.
Yield Distribution Model
Much work has been done in the field of yield modeling [11–30] and many results can be applied in
yield analysis; however, there is too much indistinctness in a modeling approach and too many disputes
about the correct model [16,17,19,23,24]. It appears that the main stumbling block was identification of
the yield defined as a probability of failure-free IC chip (the chip yield) with the yield defined as a ratio
between the number of failure-free chips n and the total number of chips N on a wafer (the wafer yield).
There is a major difference between these two quantities: the chip yield is a probability and can be expressed
by a number between 0 and 1, while the wafer yield is a stochastic variable and should be expressed by its
distribution function.
The final goal of yield modeling must be to predict the wafer yield, so as to enable comparison with
the production yield data. The authors have proposed a yield model that does not require any defect
density distribution function but is completely based on the test chip yield measurement and can predict
the wafer yield as a distribution [31].
Chip Yield
Using corresponding in-line measurements of the test chip yields Yti,
defined as a ratio between the number
of failure-free test chips and the total number of test chips in a given wafer area, the IC chip yield, associated
with the ith
critical process step, can be directly predicted. A typical test chip containing MOS capacitors,
diodes, transistors, long conducting lines, and chains of contacts is shown in Fig.47.3. The IC chip yield
will differ from the test chip yield due to the difference in the critical area. So, if a ratio between the IC
chip and test chip critical areas is given by Αci/
Αti,
and the wafer area can be divided into m subareas with
approximately uniform distribution of defects, the IC chip yield can be determined by [14,31]
© 2002 by CRC Press LLC
(47.8)
where l denotes the corresponding subarea. If a control wafer area has been divided into subareas in the
same way for each critical process step, the final IC chip yield is given by
FIGURE 47.3
Test chip containing test structures.
k
Y cil
=
Aci /Ati Ytil Ycl = ∏Y cil for l =
1, 2,…,m
i=1
D 2
/σ 2
(47.9)