U. Glaeser

FIGURE 2.34 Dual-rail, pass-transistor logic circuits.
FIGURE 2.35 BDD and other logic representations for 2-input XOR logic.
restored pass-transistor logic) shown in Fig. 2.34(a,c) [2,3,6] are effective solutions. These circuits have
both positive and negative polarities for all signals complementarily, so there is no need for an inverter
to generate complementary signals. Thus, high-speed operation becomes possible. Moreover, the differential
operation in these dual-rail pass-transistor circuits is also effective in improving the noise-margin
characteristics of the pass-transistor circuit. In addition, dual-rail PTL can still provide logic circuits with
fewer transistors than their CMOS counterparts [1,2], although it requires twice as many transistors as
a single-rail pass-transistor circuit. In this chapter, a method for synthesizing single-rail PTL is described
below, because same method can be applied to dual-rail PTL by just changing pass-transistor selector
from single-rail to dual-rail PTL.
BDD is one type of logic representation and expresses a logic function in a binary tree [21–23]. For
example, Fig. 2.35(a–c) shows three typical logic representations for 2-input XOR logic: (a) boolean
equation, (b) truth table, and (c) BDD. As shown in Fig. 2.35(c), the BDD consists of nodes and edges.
The nodes are categorized into two types: variable nodes and constant nodes of “0” or “1”. A variable
node represents a variable of the logic function. For example, node A in the BDD corresponds to the
variable A in the logic function shown in Fig. 2.35(a,b). A variable node has one outgoing edge and two
incoming edges, a 0-edge and a 1-edge. In this figure, a 0-edge is denoted by a dotted line and a 1-edge
by a straight line, although there are other representations used in BDDs. These two incoming edges
show the logic functions when the variable of the node is set to “0” and “1”, respectively. The logic
functions are represented by the connections of these elements. For example, when (A, B) is (0, 0), Out
becomes 0 in the truth table. This corresponds to selecting the 0-edge at the nodes A and B. The path
to node “0” can be traced from the root in the BDD in Fig. 2.35(c). Furthermore, the fact that there are
two cases, (A, B) = (0, 1) and (1, 0), for Out = 1 in the truth table corresponds to the fact that in the
BDD there are two paths from the root to “1”; that is, A = 0 → B = 1 and A = 1 → B = 0.
A BDD can be simplified by using complementary edges. The complementary edges are used to represent
the inverted logic of a node, as shown in Fig. 2.36(a). By using complementary edges, two nodes, B and
B,
can be combined as one node and the BDD can be simplified. For example, Fig. 2.36(b) shows a
simplified BDD with complementary edges for the BDD shown in Fig. 2.35(c).
BDDs have a good correspondence with selector logic and pass-transistor circuits, as shown in Fig. 2.37,
because the BDD represents logic functions in a binary tree structure. Thus, it is possible to generate
a pass-transistor circuit for a target logic function by replacing the nodes in the BDD with pass-transistor
selectors and connecting their control inputs with the input variables related to the nodes [10].
A detailed example how to synthesize PTL from a BDD is shown in Fig. 2.38(a–i). BDD is first
constructed for the logic functions shown in Fig. 2.38(a). The BDD can be built by recursively applying
© 2002 by CRC Press LLC
Out
C
V dd
A A A A
Out = AB + AB
(a) Boolean equation
B A
C B
(a) CPL [2]
A B
0 0
0 1
1 0
1 1
Out
Out
0
1
1
0
(b) Truth table
Out
B
A
C
Out
B
0 1
(c) BDD
B A
C B
(b) SRPL [6]
Out
1-edge
true if node = 1
0-edge
true if node = 0