U. Glaeser

FIGURE 10.80 Modeling process variations in schematic.
FIGURE 10.81 Schematic model to simulate stability, read and write noise margin.
To estimate ∆L and ∆V t, use the 3-sigma figures for the specific process. These figures are usually
obtainable from the process foundry. For example, in a typical 0.18 µm technology, 3-sigma for L and
V t are ±0.01 µm and ±20 mV. If 1 Mb memory is embedded in a die and you allow 1/1000 die to fail,
the failure rate is 1E-9. This corresponds to 6.1-sigma. ∆V t will be 40.6 mV. This mismatching is between
two supposedly matched transistors in the same circuits. All N and/or P transistors on a die may shift
from their typical characteristics to slower or faster corners. When simulating a circuit, all combination
of process corners must be considered for the worst case.
The schematic model shown in Fig. 10.81 is used to study the memory cell stability, read and write
margins. To initialize the cell, write a data into the cell and turn the word line (LWL) low. Then ramp
the V cc from, say, V cc – 0.25V cc to V cc + 0.25V cc. If the cell changes state, it is not stable. The lower and
upper V cc levels used in this test are application dependent. For upper level the burn-in voltage may be
used. This simulation must be carried out in all process corners. To improve stability, increase the width
of the ND or/and decrease the width of the pass transistor.
A read operation starts with pre-charging the bit lines. During this phase no word line (LWL) is
selected. Then a row will be selected for read. This will cause a charge sharing between the bit line and
the low side of the cell. The memory cell read margin determines how far the upset side of the cell is
from corrupting the stored data. To replicate a read operation, a current source is ramped up on the low
side of the cell. The voltage at which the cell is flipped is called the trip point of the cell. The read margin
is the trip point voltage minus 5–10% of V cc. The percentage depends on the memory environment. This
simulation must be carried out in all process corners. For good noise immunity, the read margin needs
to be between 5–10% of V cc. The same measures used to improve cell stability can also be used to improve
the read noise margin.
As in the read operation a write also starts with pre-charging the bit lines. Then a row is selected and
the bit line to write a “0” is driven low by the write circuitry. The write operation must be finished in a
pre-specified time. The write margin is an indication of the write driver strength in writing an opposite
data into a cell. For this purpose a transient simulation of the write driver, bit line, and a cell under test
is required. A weak transistor must be used for the pass transistor (NP). Then the write margin is the
trip point voltage (measured in the read operation) minus the bit line voltage at the end of the write
period. For a good noise margin the write margin must be ∼10% V cc. Again, simulation must be carried
© 2002 by CRC Press LLC
W/L
-
+
W/L+∆L
+ -
W/L-∆L
(a) Ideal (b) Weak (c) Strong
V cc
strong weak
P1 P2
s1
s2
NP1 NP2
ND1 ND2
weak strong