U. Glaeser

If C 2 exists and is large enough to make it difficult to guarantee adequate phase margin, then a thirdorder
analysis must be used. This situation may have been caused by physical constraints on the capacitor
sizes, or by attempts to minimize ω C in order to maximize the amount of reference frequency sideband
filtering. In this case, it is desirable to determine the optimal values for the other device parameters that
maximize the phase margin. The phase margin, PM, and unity gain bandwidth, ω O, where the phase
margin is maximized, can be determined from the open-loop analysis as
In order to realize the optimal value for ω O, the loop gain magnitude level must be appropriately set.
This can be accomplished by determining I CH given R, or R given I CH, using the equations
It is important to remember that all worst-case combinations of device parameters due to process,
voltage, and temperature variability must be considered since they must lead to acceptable loop dynamics
for the PLL to operate correctly under all conditions.
Advanced PLL Architectures
PLL and DLL architectures each have their own advantages and disadvantages. PLLs are easier to use in
systems than DLLs. DLLs typically cannot perform frequency multiplication and have a limited delay
range. PLLs, however, are more difficult to design due to conflicting design constraints. It is difficult to
assure stability while designing for a high bandwidth.
By using variations on the basic architectures many of these problems can be avoided. DLLs can be
designed to perform frequency multiplication by recirculating intermediate edges around the delay line [7].
DLLs can also be designed to have an unlimited phase shift range by employing a delay line that can
produce edges that completely span the clock cycle [4]. In addition, both DLLs and PLLs can be designed
to have very wide bandwidths that track the clock frequency by using self-biased techniques [8], as
discussed in “Self-Biased Techniques.”
DLL/PLL Performance Issues
To this point, this chapter section presents basic issues concerning the structure and design of DLLs and
PLLs. While these issues are important, a good understanding of the performance issues is essential to
successfully design a DLL or PLL. Many performance parameters can be specified for a DLL or PLL
design. They include frequency range, loop bandwidth, loop damping factor (PLL only), input offset,
output jitter, both cycle-to-cycle (period) jitter and tracking (input-to-output) jitter, lock time, and power
dissipation; however, the biggest performance problems all relate to input offset and output jitter.
Input offset refers to the average offset in the phase of the output clock from its ideal value. It typically
results from asymmetries between the circuits for the reference and feedback paths of the phase detector
or from charge injection or charge offsets in the charge pump. In contrast, output jitter refers to the
time-varying offsets in the phase of the output clock from its ideal value or from some reference signal
caused by disturbances from internal and external sources.
Output Jitter
Output jitter can create significant problems for an interface by causing setup and hold time violations,
which lead to data transmission errors. Consider, for example, the measured jitter histogram in Fig. 10.11.
It shows the traces of many PLL output transitions triggered from transitions on the reference input and
© 2002 by CRC Press LLC
PM 2 tan −1
= ⋅ ( ( + 1)
) – π/2
ωO = C/C2 + 1
C/C 2
( )�( R⋅C) ICH = N/KV ⋅ C2� R⋅C ( ) 2 ( C/C2 + 1)
3/2
⋅
R N/ ( ⋅ ) C2 C 2 ( C/C2 + 1)
3/2
=
⋅ ⋅ ⋅
( K V I CH