U. Glaeser

FIGURE 2.90 Pass gate leakage.
body effect, so it is necessary to take that characteristic into consideration in the circuit design of a
practical MPU.
Floating Body Effect
PD-SOI structures exhibit the kinking phenomenon, as shown in Fig. 2.89, but IBM has reported that
the most important factor in the improvement of MPU performance, in addition to reduction of the
junction capacitance and reduction of the back gate effect, is increasing the drain current due to impact
ionization. This makes use of the phenomenon in which, if the drain voltage exceeds 1.1 V, the holes
that are created by impact ionization (in the case of an n-MOSFET) accumulate in the body region,
giving the body a positive potential and thus lowering the Vth of the n-MOSFET, and thus increasing the
drain current. The increase in drain current due to this effect is taken to be 10–15%. On the other hand,
from the viewpoint of devices for application to large-scale LSI, it is necessary to consider the relation
between the MOSFET Vth and standby leak current. According to IBM, even if there is a drop in Vth due
to the floating body effect, there is no need to preset the device Vth setting for the operating voltage to
a higher value than is set for bulk Si devices in the worst case for the increase in the standby leak current,
which is to say, transistors that have the shortest gate lengths at high temperatures [15].
Next, consider the pass gate leak problem [15,20], which is shown in Fig. 2.90. In the case of an n-
MOSFET on SOI, consider the state in which the source and drain terminals are at the high level and
the gate terminal is at the low level. If this state continues longer than 1 µs, for example, the body potential
becomes roughly Vs − Vbi (where Vs is the source terminal voltage and Vbi is the built-in potential). In
this kind of state, the gate voltage is negative in relation to the n-MOSFET source and drain, and holes
accumulate on the MOS surface. If, in this state, the source is put into the low level, the holes that have
accumulated on the MOS surface become surplus holes, and the body region–source pn junction is biased
in the forward direction so that a pulsed current flows, even if the gate is off. Because this phenomenon
affects the normal operation of the access transistors of DRAM and SRAM and the dynamic circuits in
logic LSIs, circuit design measures such as providing a margin for maintenance of the signal level in SRAM
and dynamic logic circuits are required. For DRAM, it is necessary to consider shorter refresh frequencies
than are used for bulk Si devices.
Finally, we will describe the dependence of the gate delay time on the operating frequency, which is
called the history effect [15,21]. As previously described, the body potential is determined by the balance
between charging due to impact ionization and discharging through the body–source pn junction
diode, and a change in that produces a change in the MOSFET Vth as well. For example, consider the
pulse width relationship of the period of a pulse that is input to an inverter chain and the pulse width
after passing through the chain, which is shown in Fig. 2.91. The n-MOSFETs of the odd-numbered
© 2002 by CRC Press LLC
CS Discharge Current ( µ A/ µ
m)
4
3
2
1
0
1.5 V
0 V
0 1 2 3 4
Time (ns)
C S