U. Glaeser

FIGURE 9.20 Half-adder circuit.
is low because the output node has serial resistor to degrade the output signal [6], so the number of
direct connection of this gate is practically limited to two. Figure 9.19(d) is of a 7-transistor type whose
p-channel transistor is introduced to the gate of the output inverter to compensate for weak drivability
to a high level when a = b = 1 (at high level) [7].
To control the carry propagation efficiently, the following signals are defined for long-word addition
at each bit position i:
© 2002 by CRC Press LLC
a i
bi
ci-1
FIGURE 9.21 One-bit full adder.
ai bi carry-propagate signal p i = a i ⊕ b i
carry-generate signal g i = a ib i
Using these notations, Eqs. (9.36) and (9.37) are rewritten by
s i = p i ⊕ c i−1
c i = g i + p ic i−1
(9.38)
(9.39)
(9.40)
(9.41)
respectively. A carry is generated if g i = 1, and the stage i(ith bit position of an n-bit adder) propagates
an input carry signal c i−1 to its output if p i = 1. These signals are generated in a gate called a half adder
(HA) as shown in Fig. 9.20, and used to constitute a high-speed but complicated carry control scheme
such as a carry lookahead adder as described in the later sections. FA is often implemented according to
the Boolean equations (9.40) and (9.41). Though there exist many variations to constructing a FA, only
one example is shown in Fig. 9.21. In this construction, the transistor count is 30. By using pass transistor
switches, we can reduce it to 24.
Ripple Carry Adder
A ripple carry adder (RCA) is the simplest one as a parallel adder implemented in hardware. An n-bit
RCA is implemented by simple concatination of n 1-bit FAs. As the carry signal ripples bit by bit from
the least significant bit to the most significant bit, the worst-case delay time is in proportion to the number
n of 1-bit full adders [1]. This is roughly equal to the critical path delay of RCA, if n is large enough as
compared with 1.
p i
g i
si
ci