U. Glaeser

FIGURE 12.8
Design
Entry
Logic Simulation and Test
A typical FPGA CAD tool design flow is shown in Fig. 12.8. First, the design is entered, using an HDL
or schematic. Large designs are often simulated first using a faster running functional simulation tool
that uses a zero gate delay model (i.e., it does not contain any gate level timing information). Functional
simulation will detect logical errors but not synthesis related timing problems. Timing simulations are
performed later after synthesis and mapping of the design onto the FPGA.
A test bench (also called a test harness or a test fixture) is a specially written module that provides
input stimulus to a simulation and automatically monitors the output of the hardware unit under test
(UUT) [8,22]. Using a test bench isolates the test-only code portion of a design from the hardware
synthesis model. By running the same test bench code and test vectors in both a functional and timing
simulation, it is possible to check for any synthesis related problems. It is common for the test bench
code to require as much development time as the HDL synthesis model.
Following functional simulation of the design, the logic is automatically minimized, the design is synthesized,
and saved as a netlist. A netlist is a text-based representation of a logic circuit’s schematic diagram.
FPGA Place and Route Tools
An automatic fitting or place and route tool then reads in the design’s netlist and fits the design into the
device. The design is mapped into the FPGA’s logic elements, first by partitioning the design into small
pieces that fit in an FPGA’s logic element, and then by placing the design in specific logic element locations
in the FPGA. After placement, the interconnection network routing paths are determined. Many logic
elements must be connected to form a design, so the interconnect delays are a function of the distance
between the logic elements selected in the place process. The place and route process can be quite involved
and can take several minutes to compute on large designs. Combinatorial explosion prevents the tools
from examining all possible place and route assignments for a design. Heuristic algorithms such as simulated
annealing are used for place and route, so running the place and route tool multiple times may
produce better performance. External I/O signals can be constrained to particular device pin numbers, but
allowing them to be selected automatically by the place and route tools often results in improved performance.
Many tools also allow the designer to specify timing constraints on critical signal paths to help
meet performance goals. Most tools still include a floorplan editor that allows manual placement of the
design into logic elements, but current generation tools, using automatic placement with appropriate timing
constraints, are likely to produce superior performance. Place and route errors will occur when there are
not enough logic elements, interconnect, or pin resources on the specified FPGA to support the design.
After partition, place, and route, accurate timing simulations can be performed using logic and interconnect
time delays automatically obtained from the manufacturer’s detailed timing model of the device.
Although errors can occur at any step in the process, the most common step where errors are detected is
during tests in an exhaustive simulation.
Device Programming and Hardware Verification
After successful simulation, the final step is device programming and hardware verification using the
actual FPGA. Smaller PLD and CPLD devices with fuses or EEPROM will only need to be programmed
once since the memory is nonvolatile. Most FPGAs use volatile RAM memory for programming, so they
need to be reprogrammed each time power is turned on. For initial prototyping, FPGA CAD tools can
© 2002 by CRC Press LLC
Translation
Functional
Simulation
CAD tool flow for FPGAs and CPLDs.
Optimization
& Synthesis
Place &
Route
Timing
Simulation
Device
Programming