U. Glaeser

Vivek De
Intel Corporation
Ali Keshavarzi
Intel Corporation
Siva Narendra
Intel Corporation
Dinesh Somasekhar
Intel Corporation
Shekhar Borkar
Intel Corporation
James Kao
Intel Corporation
Raj Nair
Intel Corporation
Yibin Ye
Intel Corporation
16.1 Introduction
© 2002 by CRC Press LLC
16
Techniques for Leakage
Power Reduction
16.1 Introduction
16.2 Transistor Leakage Current Components
p-n Junction Reverse Bias Current (I 1) • Weak Inversion
(I 2) • Drain-Induced Barrier Lowering (I 3) • Gate-Induced
Drain Leakage (I 4) • Punchthrough (I 5) • Narrow Width
Effect (I 6) • Gate Oxide Tunneling (I 7) • Hot Carrier
Injection (I 8)
16.3 Circuit Subthreshold Leakage Current
Transistor Stack Effect • Steady-State Leakage Model of
Transistor Stacks • Transient Model of Transistor Stack
Leakage
16.4 Leakage Control Techniques
Standby Leakage Control by Input Vector
Activation • Embedded Dual-V t Design for Domino
Circuits • Adaptive Body Biasing (ABB)
Supply voltage ( Vcc)
must continue to scale down at the historical rate of 30% per technology generation
in order to keep power dissipation and power delivery costs under control in future high-performance
microprocessor designs. To improve transistor and circuit performance by at least 30% per technology
generation, transistor threshold voltage ( Vt)
must also reduce at the same rate so that a sufficiently large
gate overdrive ( Vcc/
Vt)
is maintained. However, reduction in Vt
causes transistor subthreshold leakage
current ( Ioff)
to increase exponentially. Large leakage can (1) severely degrade noise immunity of dynamic
logic circuits, (2) compromise stability of 6T SRAM cells, and (3) increase leakage power consumption
of the chip to an unacceptably large value. In addition, degradation of short-channel effects, such as
Vt
roll-off and drain induced barrier lowering (DIBL), in conventional bulk MOSFET’s with low Vt
can pose serious obstacles to producing high-performance, manufacturable transistors at low cost in
sub-100 nm Leff
technology generations and beyond. To further compound the technology scaling problems,
within-die and across-wafer device parameter variations are becoming increasingly untenable. This
nonscalability of process tolerances is also a barrier to Vcc
and technology scaling.
To illustrate the barrier associated with excessive leakage power, one can estimate the subthreshold leakage
power of future chips, starting with the 0.25 µ m technology described in [1], and projecting subthreshold