U. Glaeser

to minimize jitter, its size is constrained to less than about 1nF. The charge pump current I CH is constrained
to be greater than about 10 µA depending on the level of charge pump charge injection offsets.
The problem of selecting device parameters is made more difficult by a number of constraining factors.
First, ω N and ζ both depend on all of the device parameters. Second, the maximum limit for C and
minimum limit for I CH will impose a minimum limit on ω N, which already has a maximum limit due to
ω REF and other possible limits due to jitter and reference sideband issues. Third and most important, all
worst-case combinations of device parameters due to process, voltage, and temperature variability must
lead to acceptable loop dynamics.
Handling the interdependence between the loop parameters and device parameters is simplified by
observing some proportionality relationships and scaling rules that directly result from the equations
that relate the loop and device parameters. They are summarized in Table 10.4 and Table 10.5, respectively.
The constant frequency scaling rules can transform one set of device parameters to another without
changing any of the loop parameters. The proportional frequency scaling rules can transform one set of
device parameters, with the resistance, capacitances, or charge pump current held constant, to another
set with scaled loop frequencies and the same damping factor. These rules make it easy to make adjustments
to the possible device parameters with controlled changes to the loop parameters.
With the many constraints on the loop and device parameters established by both the system environment
and the circuit implementation, the design of a PLL typically turns into a compromise between
conflicting design requirements. It is the job of the designer to properly balance these conflicting requirements
and determine the best overall solution.
PLL Design Strategy
Two general approaches can be used to determine the device parameters for a PLL design. The first
approach is based on an open-loop analysis. This approach makes it easier to visualize the stability of the
design from a frequency domain perspective. The open-loop analysis also easily accommodates more
complicated loop filters. The second approach is based on a closed-loop analysis. This approach involves
© 2002 by CRC Press LLC
TABLE 10.4 Proportionality Relationships between PLL Loop and Device
Parameters
I CH
ω N ω C ζ ω C�ω N
0.5
ICH 0.5
indep. ICH 0.5
1/ICH R indep. 1�R R 1�R
C 1�C 0.5
indep. C 0.5
C 0.5
(C >> C2) C2 indep. 1�C2 indep. 1�C2 (C >> C2) TABLE 10.5 PLL Loop and Device Parameter Scaling Rules
Constant frequency scaling: Given x, suppose that
I CH ⋅ x → I CH
C I ⋅ x → C I
R�x → R
Then all parameters, G O, Ω I, and ζ, remain constant
Proportional frequency scaling: Given x, suppose that
I CH ⋅ x→ I CH I CH ⋅ x 2 → I CH I CH→ I CH
C I/x→ C I C I→ C I C I�x 2 → C I
R→ R R�x→ R R ⋅ x→ R
Then, Then,
G O→ G O
ω I ⋅ x→ ω I
ω C/ω N→ ω C/ω N
ζ→ ζ
where C I represents all capacitors and ω Ι represents all frequencies.
s