U. Glaeser

FIGURE 12.5
dimensional array on the chip. Current FPGAs contain a few hundred to over a hundred thousand logic
elements. To perform complex operations, logic elements can be automatically connected to other logic
elements on the chip using a programmable interconnection network. The programmable interconnection
network is also contained in the FPGA.
The interconnection network used to connect the logic elements contains row and column chip-wide
interconnects. In addition, the interconnection network usually contains shorter and faster programmable
interconnects limited only to neighboring logic elements. The internal interconnect delays are an important
performance factor since they are of the same order of magnitude as the logic element delay times.
Using a shorter interconnect path means less delay time. So that high-speed adders can be produced,
there is often a dedicated fast carry logic connection to neighboring logic elements.
Clock signals in large FPGAs must use special low-skew global clock buffer lines. These are dedicated
pins connected to special internal high-speed busses. These special busses are used to distribute the clock
signal to all flip-flops in the device at the same time to minimize clock skew. If the global clock buffer
lines are not used, the clock is routed through the chip just like a normal signal. The clock signals could
arrive at flip-flops at widely different times since interconnect delays will vary significantly in different
parts of the chip. This delay time or clock skew may violate flip-flop setup and hold times. This causes
metastability or unpredictable operation in flip-flops. Most large designs with clock signals that are used
throughout the FPGA will require the use of the global clock buffers. Some CAD tools will automatically
detect and assign clocks to the global clock buffers and others require designers to identify clock signals
and assign them to one of the global clock buffers.
General purpose external I/O pins on CPLDs and FPGAs contain programmable bidirectional tristate
drivers and flip-flops. Pins can be programmed for input, output, or bidirectional operation. The I/O
signal can be loaded into the I/O pin’s flip-flop or directly connected to the interconnection network
and routed from there to internal logic elements. Multiple power and ground pins are also required on
large CPLDs and FPGAs. FPGA internal core voltages range from 1.5 to 5 V. FPGAs using advanced
package types such as pin grid array (PGA) and ball grid array (BGA) are available with several hundred
pins.
When a design approaches the device size limits, it is possible to run out of either logic, interconnect,
or pin resources when using a CPLD or FPGA. CPLD and FPGA families include multiple devices in a
wide range of gates with varying numbers of pins available on different package types. To minimize cost,
part of the design problem is selecting a device with just enough logic, interconnect, and pins. Another
important device selection factor is the speed or clock rate needed for a particular design.
© 2002 by CRC Press LLC
Inputs from
Interconnect
Network
DATA1
DATA2
DATA3
DATA4
CLR1
CLR2
Chip-Wide
Reset
CLK1
CLK2
Look-Up
Table
(LUT)
Clear/Preset
Logic
Clock Select
Typical FPGA logic element.
Carry
In
Carry
Chain
Carry
Out
Register Bypass
PRN
D Q
ENA
CLRN
Programmable
Register
To Row/Col
Interconnect
Network
To Local
Interconnect
Network
This denotes a control input
provided by the FPGA s SRAM
programming data