U. Glaeser

FIGURE 10.85 Bit line twisting to reduce coupling capacitans and read time data dependency.
Readsel
SenSel
FIGURE 10.86 Three popular sense amplifiers: (a) Current mirror based, (b) Latch with positive feedback, and
(c) Dual slope or/and clocked V cc.
to the bit line adds a certain amount of capacitance to the bit line. Junction capacitance is the main
source of bit line capacitance. Choosing the number of cells per column is an important design decision
as it determines the speed, power consumption, area efficiency, and hence, the architect of the memory.
In a typical 0.18 µm technology 256–512 cells per bit line is a good compromise. Bit line to bit line
coupling is a major source of mismatching. Its contribution to bit line capacitance is also significant and
is the only component that circuit designers can influence.
Coupling capacitance between bit lines has two consequences. It increases the total capacitance and
makes the read time data dependent. Adjacent cells to a cell may have different data for two reads of the
same cell. The strategy to reduce the bit line coupling capacitance is to twist the bit line along long run
of bit lines. Figure 10.85(a) shows a simple strategy in which the coupling between bit lines is completely
cancelled; however, the coupling between Bit and Bit# of the same cell is not cancelled. But signal shifting
due to this coupling is deterministic and limited. In modern CMOS process technologies, it is possible
to use higher level of metals for bit lines to lower the line to substrate capacitance. It is also made
possible that to run, in addition to bit lines, a supply line through the cell. This supply line not only
helps to have a power mesh in the memory, it also can be used to cancel the Bit to Bit# coupling, see
Fig. 10.85(b). Twisting the bit lines degrades the area efficiency of the memory. If the supply line is
drawn outside the bit lines, the strategy in Fig. 10.85(c) may be used to increase the area efficiency and
live with the known Bit to Bit# coupling capacitance.
Many different sense amplifiers circuits are used in memory design. Two most popular circuits are considered
here. The miller current mirror sense amplifier, Fig. 10.86(a), is used in more conservative and slow
designs. The SenSel signal is asserted after enough differential signals are developed on the bit lines. The main
© 2002 by CRC Press LLC
b0 b0# b1 b1 #b2 b2# b0 b0# b1 b1# b2 b2# b0 b0# b1 b1# b2 b2#
v ss
v ss
v ss
v ss
(a) (b) (c)
Bit Bit#
v ss
Bit Bit#
Bit
ΦL Bit#
P1 P2
V1 V2
N1 N2
P1 P2
V1 V2
N1 N2
SenSeld
(a) (b) (c)