U. Glaeser

FIGURE 2.22 CMOS SRAM cell with read amplifier and data write circuitry [6].
the row select signal is applied, the voltage level on complementary bit line C′ drops slightly because it
is pulled down by T2 and T4. The data read circuitry detects the small voltage difference between C and
C′ lines (C is higher) and amplifies it as logic “1” output. The data read circuitry can be constructed as
a simple source-coupled differential amplifier or as a differential current-mirror sense amplifier circuit
(as indicated in Fig. 2.22). The current-mirror sense amplifier achieves a faster read time than the simple
source-coupled read amplifier. The read access speed can be further improved by two- or three-stage
current mirror differential sense amplifiers [6].
Dynamic RAM Circuits
All RAMs lose their contents when power supply is turned off. However, some RAMs gradually lose the
information even if power is not turned off, because the information is held in a capacitor. Those RAMs
need periodic refreshing of information in order to retain the data. They are called dynamic RAMs or
DRAMs.
Static RAM cells require 4–6 transistors per cell and need 4–5 lines connecting to each cell including
power, ground, bit lines, and word lines. It is desirable to realize memory cells with fewer transistors and
less area, in order to construct high density RAM arrays. The early steps in this direction were to create
a 4-transistor cell as in Fig. 2.23(a) by removing the load devices of the 6-transistor SRAM cell. The data
is stored in a cross-coupled transistor pair as in the SRAM cells we discussed earlier. But it should be
noted that voltage from the storage node is continuously being lost due to parasitic capacitance, and
there is no current path from a power supply to the storage node to restore the charge lost due to leakage.
Hence, the cell must be refreshed periodically. This 4-transistor cell has some marginal area advantage
over the 6-transistor SRAM cell, but not any significant advantage. An improvement over the 4-transistor
DRAM cell is the 3-transistor DRAM cell shown in Fig. 2.23(b). Instead of using a cross-coupled transistor
pair, this cell uses a single transistor as the storage device. The transistor is turned ON or OFF depending
© 2002 by CRC Press LLC