U. Glaeser

FIGURE 44.4
FIGURE 44.5
It becomes evident that the isolation approach and the techniques to make a core test-ready depends
on various design constraints such as area, timing, power as well as the test coverage needs for the core,
and the core interconnect faults.
Core Test Integration
Testing SoC devices with multiple blocks (Fig. 44.4), each block embedding different test techniques,
could become a nightmare without an appropriate test manager that can control the testing of various
blocks. Some of these blocks could be user-designed and others predesigned cores. Given the current
lack of any test interface standard in the SoC environment, it becomes very complex to control and observe
each of the blocks. Two key issues must be addressed: sequencing of the test operations [4] among the
various blocks, and optimization of the test interface between the various blocks and the chip I/O. These
depend very much on the test architecture, whether test controllers are added to individual blocks or
shared among many, and whether the blocks have adopted differing design-for-test (DFT) methodologies.
A high-level view of the SoC test architecture is shown in Fig. 44.5, where the embedded test in each of
the cores is integrated through a test bus, which is connected to a 1149.1 TAP controller for external
access. Many devices are using boundary scan with the IEEE 1149.1 TAP controller not only to manage
in-chip test, but also to aid at board and system-level testing. Some of the test issues pertain to the use
of a centralized TAP controller or the use of controller in each block with a common test bus to
communicate between various test controllers. In other words, it is the question of centralized versus
distributed controller architecture. Each of these has implications with respect to the design of test
functionality within each block.
Besides testing each core through their individual access mechanism such as the core isolation wrapper,
the complete testing of the SoC also requires an integrated test which tests the interconnects between
the cores and the user-defined-logic (UDL). The solution requires, first to connect the test facilities
© 2002 by CRC Press LLC
DRAM
User
Logic
Core
An SoC includes multiple cores with memory and user logic.
User-Logic
Core
Wrapper
SRAM Core
Core
on-chip Test Controllers
Core
wrapper
Test Bus
1149.1 TAP
A high-level architecture for SoC test integration.
R
O
M
User
Logic
D/A-A/D
Core
wrapper
on-chip BIST controllers
SoC