U. Glaeser

Look-up
for r7
FIGURE 6.12 Methods for keeping track of the actual mapping of architectural registers to rename buffers. (RB
designates rename buffer.)
mapping within the rename buffers themselves. In the following section we outline these methods,
illustrated in Fig. 6.12.
A mapping table has as many entries as there are architectural registers in the instruction set architecture
(ISA), usually 32. Each entry holds a status bit (called the entry valid bit in the figure), which indicates
whether the associated architectural register is renamed. Each valid entry supplies the index of the rename
buffer, which is allocated to the architectural register belonging to that entry (called the RB-index). For
instance, the left side of Fig. 6.12 shows that the mapping table holds a valid entry for architectural
register r 7, which contains the RB-index of 12, indicating that the architectural register r 7 is actually
renamed to rename buffer number 12. As already indicated, usually each entry is set up during instruction
issue while new rename buffers are allocated to the issued instructions. A valid mapping is updated when
the architectural register belonging to that entry is renamed again, and it will be invalidated when the
instruction associated with the actual renaming completes. In this way, the mapping table continuously
holds the latest allocations. Source registers of issued instructions are renamed by accessing the mapping
table with the register numbers as indices and fetching the associated rename buffer identifiers (RB-indices),
as shown in Fig. 6.12.
We note that for split architectural register files obviously separate FX- and FP-mapping tables are
needed.
Mapping tables should provide one read port for each source operand that may be fetched in any one
cycle, and one write port for each rename buffer that may be allocated in any one cycle (as discussed
earlier in the section on “Number of Read and Write Ports”).
The other fundamentally different alternative for keeping track of the actual register mappings relies
on an associative mechanism (see the right side of Fig. 6.12). In this case no mapping table exists but
each rename buffer holds the identifier of the associated architectural register (usually the register number
of the renamed destination register) and additional status bits as well. These entries are set up usually
during instruction issue when a particular rename buffer is allocated to a specified destination register.
As Fig. 6.12 shows, in this case each rename buffer holds five pieces of information: (1) a status bit, which
indicates that this rename buffer is actually allocated (called the entry valid bit in the figure), (2) the
identifier of the associated architectural register (Dest. reg. no.), (3) a further status bit, called the latest
© 2002 by CRC Press LLC
0
5
6
7
8
Using a
mapping table
Entry
valid
RB
index
Mapping
table
1
0
1
1
7
12
14
"12"
(RB index = 12)
Method for keeping track of the
actual register mapping
Assoc.
look-up
for r7
0
9
10
11
12
Entry
valid
Dest.
reg. nr.
Mapping within
the rename buffers
Latest
bit
Value
Rename buffers
Value
valid
1 8 1
80
1
1 7 0
7
1
1 9 1
-
0
1 7 1 70 1
"12"
(RB index = 12)