U. Glaeser

inverters, and the programmable multiplexors. The inverters provide almost all combinations of normal
and inverted direct output or latched signals synchronized with direct or inverted clocks: this avoids the
need to use resources in the CLBs simply to invert signals. Limited slew rate control was also added to
the output buffers—a precursor to the support for multiple electrical protocols now found in more modern
designs.
Additional Features
Adders, including counters, occur on the critical paths in many calculations, so the 4000 series, like most
of its modern counterparts, provides “fast-carry” logic. Ripple carry adders are simple, regular, and use
minimal logic, but they must wait until a carry bit has “rippled” through all the summing (full adder)
blocks. By providing a fast, direct path for carry bits between blocks, the critical delay in a ripple carry
adder is significantly reduced. The fast carry logic is so effective that there is no advantage to be gained
from more complex adders, such as carry-lookahead ones. A carry-lookahead adder requires a much
larger number of CLBs and the signal propagation times between these additional CLBs outweigh any
benefit to be gained from a complex adder: trials with carry-lookahead adders show them to be slower
than ripple carry adders that use the fast-carry logic [6].
The special needs of global clocks are addressed by providing “semi-dedicated” I/O pads connected
to four primary global buffers designed for minimum delay and skew. The clocks of each CLB can be
connected to these global buffers, a set of secondary buffers or any other internal signal. Thus multiple
global and local clock domains can be established.
Problem diagnosis and boundary scan testing is facilitated through support for IEEE 1149.1 (JTAG)
boundary scan logic attached to each I/O buffer.
The CLB structure lends itself to efficient implementation of functions of up to 9 inputs, but address
decoders commonly require many more bits. Special decoders accepting up to 132 bits for large XC4000
devices are provided to ensure fast, resource-efficient decoding.
A simple internal oscillator and divider provides clock signals when precise frequencies are not required.
Virtex
The Virtex family [5] are enhanced versions of the Xilinx 4000 series. Improved process technology has
6
allowed the gate capacity to exceed one million (4 × 10 are claimed for the largest member of the family,
requiring 2 MB of configuration data). Supply voltages as low as 1.8 V allow internal clocks up to 400 MHz
to be used.
Memory
Blocks of dedicated memory are now provided, which can be programmed to a number of single- and
dual-port configurations. This will allow considerable performance enhancements for designs which were
previously forced to use external memory.
I/O Buffers
One of the most dramatic additions to the newest devices from all manufacturers is the support of
numerous electrical protocols at the I/O pins. For example, Virtex supports single-ended standards:
LVTTL, LVCMOS, PCI-X, GTL, GTLP, HSTL, SSTL, AGP-2X and differential standards: LVDS, BLVDS,
ULVDS, LDT, and LVPECL. Support for PCI-X means that a Virtex device can implement the industrystandard
PCI interface, considerably reducing the complexity of PCI cards which can now combine
interface logic, control logic, some memory, and external bus interfaces (e.g., LVDS) in a single chip.
Virtex devices are also partially reconfigurable: individual columns may be reprogrammed.
Algotronix
3
Algotronix’s approach to FPGA design was radically different from the Xilinx approach. Cells were much
simpler and used for routing as well as logic.
The basic cell in shown in Fig. 37.4. By using a much simpler
cell, it becomes possible to fit more logic per silicon die and the XC6264 device [7] was rated as containing
3
However, Algotronix was taken over by Xilinx and its devices appeared as the Xilinx XC6200 series [7].
© 2002 by CRC Press LLC