U. Glaeser

FIGURE 16.11 Four-input NAND NMOS stack.
yields the current through each transistor being the same and being identically equally to the overall
stack current.
To calculate the overall leakage of the stack we use Eq. (16.1) to determine the leakage through a
transistor as a function of the drain to source voltage. This yields the voltage across second transistor
from the top as
Additionally the voltage of the rest of the transistors can be expressed in a recursive fashion. The drain
to source voltage of the ith transistor can be expressed in terms of the (i − 1)th transistor.
With the drain to source transistor voltages known, the leakage current through the stack can be computed
by finding the leakage of the bottom transistor of the stack from the subthreshold equation. An identical
method applies to the solution of leakage current for PMOS stacks. An estimate of leakage in transistor
stacks was first presented by Gu and Elmasry [13]. The above analysis for transistor stack leakage was
first presented by Johnson [14]. An early implementation of this idea for actively reducing leakage in
word decoder-driver circuits for RAMs is presented by Kawhara [15]. The term “self-reverse biasing”
used in this paper, gives a clear indication of the mechanism by which leakage of a stack of transistors
is reduced.
Transient Model of Transistor Stack Leakage
When stacked devices are turned off, the time required for the leakage currents to settle to the previously
computed steady-state leakage levels can be large and can vary widely, ranging from microseconds to
milliseconds. The settling time is important for determining if the quiescent leakage current model is
applicable. The worst-case settling time for a stack occurs when all the internal nodes are charged to the
maximum possible value V DD − V T just before every transistor of the stack is turned off. We notice that a
strong reverse gate bias will now be present for all devices except for the bottom-most device. In the figure,
MN1 to MN3 will have a reverse gate bias and the leakage through them is small. Hence, we approximate
the discharge current of the drain node of MN4 as being the leakage current of MN4 alone. Once the drain
voltage of MN4 is sufficiently small, MN3 discharges its drain node with a discharge current, which is
the leakage current of the two stacked devices MN3 and MN4. The discharge time of each internal
node of the stack, t disi, is sequential and the overall settling time is the sum of the discharge times.
© 2002 by CRC Press LLC
V DSi
V DS2
VG1=0 V
VG2=0 V
VG3=0 V
VG4=0 V
MN1
MN2
MN3
MN4 Vq3 = 14mV
nV DD
nvT -------------------------------- ln
( 1+ 2η + γ ′ )
A ------------- ⎛ 1 nv ⎛----- ⎞
⎞
T
=
⎜ e + 1
⎝
⎝A⎠ ⎟
2 ⎠
– 1
nvT ------------------ ln 1
( 1 + γ ′ )
A -----
⎛ i – 1 ⎛ v ⎞⎞
T
=
⎜ + --------- ⎜1– e VDS ( i−1 ) ⎟⎟
⎝ Ai ⎝ ⎠⎠
Vq2 = 34mV
Vq1 = 89mV
V ds1 = 1.41V
V ds2 = 55mV
V ds3 = 20mV
V ds4 = 14mV