U. Glaeser

FIGURE 10.46 Min-timing diagrams for nonoverlapping dual-phase, latch-based design.
FIGURE 10.47 Min-timing diagrams for nonoverlapping dual-phase, latch-based design under the presence of late
clock skew.
The presence of clock skew in this design makes min-timing worse also, as expected. The effect of late
clock skew is to increase the effective hold time of the sending latch. This is illustrated in Fig. 10.47,
where clock CK′ B is late with respect to CKA. The min-timing condition is given by
which can be rearranged as
© 2002 by CRC Press LLC
CK A
CK B
D 2
Q 2
D 2 ′
Q 2 ′
D 2 ″
Q 2 ″
CK A
CK B ′
D 2
Q 2
D 2 ′
Q 2 ′
T ON
Transparent
Opaque Transparent
TSETUP T THOLD TCKQTMIN Blockage
Opaque
T NOV
T NOV
Transparent
TSKEW Opaque
T CKQ T MIN
Blockage
Transparent
T HOLD
T CKQ T MIN
Opaque
TNOV + TCKQ + Tmin > Tskew + Thold Tmin >
Thold – TCKQ + Tskew – TNOV (10.18)
(10.19)
Comparing with Eq. 10.16, notice that the transparent period (T ON) is missing from the right-hand
side of Eq. (10.19), reducing the requirement on T min, and that the nonoverlap time (T NOV) gets subtracted
from the clock skew (T skew). The latter gives designers a choice to trade-off between T ON and T NOV by
increasing T NOV at the expense of T ON (so the clock cycle remains constant), min-timing problems can
be minimized at the cost of reducing time borrowing. For a sufficiently long T NOV, the right hand side
of Eq. 10.19 becomes negative. Under such assumption, this type of design may be considered race free.
Furthermore, by making the nonoverlap time a function of the clock frequency, a manufactured chip is