U. Glaeser

The efficiency of this process is dependent on the availability of a fast multiplier, since each iteration
of Eq. (9.32) requires two multiplications and a subtraction. The complete process for the initial estimate,
three iterations, and the final quotient determination requires four subtraction operations and seven
multiplication operations to produce a 16-bit quotient. This is faster than a conventional non-restoring
divider if multiplication is roughly as fast as addition, a condition which may be satisfied for systems
which include hardware multipliers.
Floating-Point Arithmetic
Recent advances in VLSI have increased the feasibility of hardware implementations of floating point
arithmetic units. The main advantage of floating point arithmetic is that its wide dynamic range virtually
eliminates overflow for most applications.
Floating-Point Number Systems
A floating point number, A, consists of a significand (or mantissa), Sa, and an exponent, Ea. The value
of a number, A, is given by the equation:
© 2002 by CRC Press LLC
A = Sa r Ea (9.34)
where r is the radix (or base) of the number system. Use of the binary radix (i.e., r = 2) gives maximum
accuracy, but may require more frequent normalization than higher radices.
The IEEE Std. 754 single precision (32-bit) floating point format, which is widely implemented, has
an 8-bit biased integer exponent which ranges between 1 and 254 [20]. The exponent is expressed in
excess 127 code so that its effective value is determined by subtracting 127 from the stored value. Thus,
the range of effective values of the exponent is −126 to 127, corresponding to stored values of 1 to 254,
respectively. A stored exponent value of ZERO (E min) serves as a flag for ZERO (if the significand is ZERO)
and for denormalized numbers (if the significand is non-ZERO). A stored exponent value of 255 (E max)
serves as a flag for infinity (if the significand is ZERO) and for “not a number” (if the significand is nonzero).
The significand is a 25-bit sign magnitude mixed number (the binary point is to the right of the most
significant bit and is always a ONE except for denormalized numbers). More detail on floating point formats
and on the various considerations that arise in the implementation of floating point arithmetic units are
given in [7,21]. The IEEE 754 standard for floating point numbers is discussed in [22,23].
Floating-Point Addition
A flow chart for floating point addition is shown in Fig. 9.18. For this flowchart, the operands are assumed
to be “unpacked” and normalized with magnitudes in the range [1/2, 1). On the flow chart, the operands
are (E a, S a) and (E b, S b), the result is (E s,S s), and the radix is 2. In step 1 the operand exponents are
compared; if they are unequal, the significand of the number with the smaller exponent is shifted right
in step 3 or 4 by the difference in the exponents to properly align the significands. For example, to add
the decimal operands 0.867 × 10 5 and 0.512 × 10 4 , the latter would be shifted right by one digit and
0.867 added to 0.0512 to give a sum of 0.9182 × 10 5 . The addition of the significands is performed in
step 5. Steps 6–8 test for overflow and correct, if necessary, by shifting the significand one position to
the right and incrementing the exponent. Step 9 tests for a zero significand. The loop of steps 10–11
scales unnormalized (but non-ZERO) significands upward to normalize the result. Step 12 tests for
underflow.
Floating point subtraction is implemented with a similar algorithm. Many refinements are possible to
improve the speed of the addition and subtraction algorithms, but floating point addition and subtraction
will, in general, be much slower than fixed-point addition as a result of the need for operand alignment
and result normalization.