U. Glaeser

29.2 Power Dissipation in Digital Circuits
This section provides a brief overview of power dissipation basics to render this document self-contained.
Four major sources of power dissipation are used in digital circuits:
• Switching or dynamic power (Psw) • Short-circuit or direct-path power (Psc) • Leakage power (Pleak) • Static power (Pstat) The total chip power is given by the following Eq. (29.1):
© 2002 by CRC Press LLC
(29.1)
The switching power dissipation is the dominant component and is due to the charging and discharging
of all capacitive nodes in the circuit. It is given by Eq. (29.2):
(29.2)
where a is the switching activity (0 ≤ a ≤ 1),
C is the total capacitance of all capacitive nodes in the circuit,
VDD
is the supply voltage, and f is the clock frequency. In case the internal nodes of the circuit do not
experience a full voltage swing from 0 V to , Eq. (29.2) is modified as follows:
V
DD
(29.3)
where Vswing
is the low voltage swing.
Short-circuit power ( Psw)
is dissipated when there is a transient direct path from VDD
to ground during
switching: During the rising (or falling) transition of static CMOS gates from VTN
to VDD
– VTP
( VDD
–
VTP
to VTN)
a direct path from VDD
to ground exists through a PMOS and NMOS stack that are both in
their ON region. If the rise and fall times of the digital circuit are kept well under control (a small fraction
of the period), short-circuit power is rarely a design issue. A comprehensive analysis on short-circuit
power in static CMOS circuits can be found in [3].
Two main types of leakage power are available. The first is subthreshold leakage and involves finite
channel conductance in the NMOS and PMOS OFF regions. The second is reverse bias junction leakage
and it involves source and drain-to-substrate PN junction leakage. Figure 29.1 shows the subthreshold
and junction leakage components.
The subthreshold current is typically the dominant component of leakage power. Low-voltage process
technologies that rely on reduced threshold voltages to maintain performance are especially susceptible
to increased subthreshold leakage. Threshold reduction results in large increases in leakage currents as
Idsat a percentage of device. Leakage currents can be especially important in low activity embedded DSP
systems (i.e., pagers) that are mostly in standby mode. In such cases, system battery life is mainly dependent
on Pleak. Techniques for reducing Pleak include the use of multiple VT
devices (MTCMOS) [4] and
substrate bias control variable threshold CMOS [5]. Commercial signal processors use such techniques
for leakage reduction [6].
FIGURE 29.1
Leakage current components.
Ptotal = Psw + Psc + Pleak + Pstat P sw
P sw
=
=
Subthreshold
Current
2
aCVDD f
aCV DDV swing f
Reverse Bias
Junction
Leakage
Current