U. Glaeser

FIGURE 13.1 High-performance microprocessor frequency projection. 1,2
FIGURE 13.2 Frequency projection in ITRS gate delay units.
13.1 The Processor Implementation Performance Food-Chain
Performance of high-frequency processor designs is becoming increasingly centered around interconnect.
Thus, designing for high frequency is largely a matter of interconnect engineering. The importance of
optimizing designs by optimizing wiring will continue to accelerate.
Device placement determines interunit and global wiring. The electrical characteristics of this wiring
and expected loads, in turn, determine the size of macro output drivers and global buffers. The sizes of
these drivers and buffers coupled with the cycle time constraints determine the device sizes, transistor
topologies, and combinational logic gate designs. These characteristics influence the size of the macros,
which affects the placement. The combinational circuits also determine the topologies, size, and placement
of latches. The latches and, in some designs, the combinational logic circuits determine the clock
generation and distribution. The circuits drive the design of the power distribution. The delay, power,
and noise susceptibility characteristics of the available topologies for logic circuits determine the arithmetic,
which can be supported in a design. The same characteristics for memory circuits determine which
latches, registers, SRAM arrays, and DRAM arrays can be supported in a design. Although the design of
high-frequency processors is a complex process, one in which performance can be lost at any stage, the
basis of the process is placement and routing.
© 2002 by CRC Press LLC
MPU frequency (MHz)
MPU cycle (gate delay units)
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0
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local clock global clock
1999 2000 2001 2002 2003 2004 2005
global clock local clock
1999 2000 2001 2002 2003 2004 2005