U. Glaeser

The interconnections between the various SoCs and the memory chips are the major paths for crosstalk
and other types of signal distortion. Reducing the routing length of the connection will help to increase
the operation speed. This can be achieved with a chip-on-chip (CoC) module. The metal redistribution
layers were fabricated on the top of the processor and the two memory chips, while the original bond
pads still remained for the wire bonding to the substrate. The memory chips can be mounted on the top
of the processor using flip-chip technology. Redistribution layers have been used to replace the bond
wires and traces on the substrate to provide the interconnections between memory chip and processor.
Since Know Good Die memory chips are usually used, testing only requires open/short test between the
processor and memory chips. No burn-in and extensive memory tests are required, so the connection
to the package ball can be removed as a new test program is implemented with the open/short test of
the memory interface through other IO paths of the VGA processor.
Summary
The broadband access, infrastructure, carrier, and enterprise Communication SoCs will demand higher
MIPS, integration, and memory bandwidth. They will also demand lower latency, power dissipation, and
cost/channel or function. Comm. SoC utilizes programmable DSP, hardwired DSP accelerators, and I/O
to implement Comm. protocols and systems in a highly integrated form. Higher memory access frequency,
DSP interface speeds, and specialized analog functions will demand the integration of Comm.
SoCs on Comm. MCM
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© 2002 by CRC Press LLC