U. Glaeser

FIGURE 46.9
FIGURE 46.10
behavioral level. Furthermore, the testable description can be synthesized using several libraries and
tools. The testable design is consequently more portable.
Moreover, when a scan chain is inserted at the
high level of the DUT, the added logic used for the test is globally compiled and optimized during the
synthesis process, which reduces the area overhead.
Fig. 46.9 shows the classical approach of scan insertion. Fig. 46.10 shows how scan can be inserted
before the synthesis is performed.
To insert a scan register at a behavioral level (high-level scan), memory elements of the DUT need to
be known. In fact, the scan insertion process is made up of two basic steps. First, memory elements are
located. Then, the behavioral description of the design is modified in order to describe the behavior of
the scan register.
Such a new scan insertion approach necessitates the development of the related tools. Hiscan (highlevel
scan) is a tool that allows scan insertion at the B-VHDL level. Given a synthesizable B-VHDL
description, Hiscan generates a VIF (VHDL intermediate format) file, which contains necessary information
of objects (signals and variables). Hiscan uses the VIF file to locate objects that correspond to
memory elements once the synthesis is accomplished. Before constructing a B-VHDL scan chain, Hiscan
considers constraints which can be used in the selection of the detected memory elements. Typically,
constraints are related to testability measures at the B-VHDL level or ATPG-based constraints or both.
During the last step, Hiscan generates a B-VHDL scannable description, which is ready for synthesis.
Given several examples of benchmarks, such a high-level scan insertion approach was shown efficient
since the cost of inserting a scan design is significantly reduced when compared to classical scan techniques
that operate at a low-level design. Please refer to [10] for more details.
© 2002 by CRC Press LLC
Low-level scan.
High level description
High-level scan.
Low level description
Synthesis tool
scan_out
Z< = A3;
A3< = scan_in ;
when others =>
if CK =’1’ ’ and CK’event then
A3 < = A1or A2;
Z< = A1and A3;
end if;
end case;
end process;
High level description
Scan insertion
tool
Low level description
process (CK)
begin
if CK=’1’and CK’event then
A3