U. Glaeser

This static current is obviously undesirable, but it does not exist for true CMOS logic. This is one of the
main reasons for the popularity of CMOS in low power applications.
Another situation that can lead to static power dissipation in CMOS is when a degraded voltage level
(e.g., the “high” output level of a nMOS pass transistor) is applied to the inputs of a CMOS gate. A
degraded voltage level may leave both the nMOS and pMOS transistors in a conducting state, leading to
continuous flow of short-circuit current. This again is undesirable and care should be taken to avoid it
in practice.
Reducing Power Consumption
The capacitive switching power (P switching), as given by the formula in Eq. (14.1), is the dominant source
of power consumption in CMOS circuits today. Research and design efforts aimed at low power are
therefore largely focussed on reducing P switching. The parameters in its formula V dd, f, C, N provide avenues
for power reduction. The idea is to either reduce each of the parameters individually without adversely
impacting the others, or to trade them off against each other.
It should be noted that f is also a measure of the performance (speed) of a system. Therefore, reduction
in power through simply a reduction in f is an option only if it is acceptable to trade off speed for power.
Power is proportional to the square of V dd. This makes reduction in V dd as the most effective way for
power reduction. This has motivated the acceptance of 3.3 V as the standard supply voltage, down from
5 V. The downward trend in V dd continues, with processors with 1.5 V internal supply voltage and lower,
already being shipped.
The problem with reducing V dd is that it leads to an increase in circuit delay. Circuit delay is inversely
proportional to V dd as a first order of approximation. The increased delay can be overcome if device
dimensions are also scaled down along with V dd. In particular, in constant-field scaling, V dd and the
horizontal and vertical dimensions of devices are scaled down by the same factor k. This is done in order
to maintain constant electric fields in the devices. To the first order of approximation, the power consumption
scales down by k 2 , and the delays go up by k. Reducing device dimensions (or feature size reduction)
is a very costly proposition, requiring changes in fabrication technology and semiconductor processes.
The other problem is that circuit delay actually rises rapidly as V dd approaches the threshold voltage
V t. As a general rule, V dd should be larger than 4V t, if speed is not to suffer excessively V t does not scale
easily and, therefore, reducing V dd below V t will be difficult.
The speed degradation (increase in delay) may be reduced by circuit technologies that allow lower V t;
however, decrease in V t leads to a significant increase in subthreshold leakage current—every 0.1 V
reduction in V t raises subthreshold leakage current by a factor of 10.
A tradeoff is involved in choosing a very low V dd. Some design options in this regard are to either
dynamically vary V t (lower V t when the circuit is active, higher when it is not) or using different V t for
sub-circuits with different speed requirements. The speed degradation may also be compensated for by
increasing the amount of parallelism in the system. This works well for applications such as digital signal
processing, where throughput is used as the performance metric.
It is also worth noting that V dd reduction only provides temporary relief in the course of technological
change. Please refer back to Fig. 14.1 and Table 14.1. These processors shown represent recent data points
for a trend that has persisted for over 25 years—increased performance through higher clock frequencies
or increased number of transistors, or both. This, however, directly increases the power consumption.
Reductions in supply voltage and feature size do help to offset the effect of increased clock frequency
and to reduce power.
For example, the original Intel Pentium processor had 0.8 µm feature size, 5 V supply voltage, 66 MHz
clock frequency, and 16 W power consumption. Reduction in the feature size to 0.5 µm and voltage to
3.3 V, led to 10 W power consumption, even at 100 MHz. But such reductions are only temporary, since
the march toward increased clock frequencies shows no signs of slowing. Thus, the power consumption
of the 200 MHz Pentium climbed back to 17 W.
© 2002 by CRC Press LLC