U. Glaeser

FIGURE 10.48 Complementary dual-phase, latch-based design.
guaranteed to work correctly at some lower than nominal frequency, even in the event that unexpected
min-timing violations are discovered on silicon. This is the most important characteristic of this type of
latching design, and the main reason why such designs were so popular before automated timing verification
became more sophisticated.
Although min-timing constraints are greatly reduced in a two-phase, nonoverlapping latch-based
design, designers should be aware that the introduction of an additional latch per stage results in twice
as many potential min-timing races that need to be checked in contrast to a single latch design. This
becomes a more relevant issue in a two-phase, complementary latch-based design, as discussed next.
Complementary Dual-Phase, Latch-Based Design
A two-phase, complementary latch-based design (Fig. 10.48) is a special case of the generic nonoverlapping
design, where clock CKA is a 50% duty cycle clock, and clock CKB is complementary to CKA. In such a
design, the nonoverlapping time between the clock phases is zero. The main advantage of this approach
is the simplicity of the clock generation and distribution. In most practical designs, only one clock phase
needs to be globally distributed to all sub-units, generating the complementary clock phase locally.
Max-timing
Similar to a nonoverlapping design, the maximum propagation delay is given by Eq. (10.17), and it is
unaffected by the clock skew. The pipeline overhead is 2T DQ.
Time Borrowing
Time borrowing is similar to a single-phase latch, except that T ON is half clock cycle. Therefore, maximum
time borrowing is given by
So complementary clocks maximizes time borrowing.
© 2002 by CRC Press LLC
Sending
Latch
D1 Q Max Path
1
Middle
Receiving
Latch
Latch
D1 ′ Q1 ′ Max Path D1 ″ Q1 ″
D2 Q2 D2 ′ Q1 ′ D2 ″ Q2 ″
Min Path
Min Path
CK
CK
Tborrow = TCYC/2 – ( Tsetup + Tskew) (10.20)
Min-timing
The min-timing requirement is similar to the nonoverlapping scheme, except that T NOV is zero. Therefore,
Tmin >
Thold – TCKQ + Tskew (10.21)
The simplification of the clocking scheme comes at a price though. Although Eq. (10.21) is less stringent
than Eq. (10.16) (no T ON in it), it is not as good as Eq. (10.19). Furthermore, a min-timing failure in
such a design cannot be fixed by slowing down the clock frequency, making silicon debugging in such a
situation more challenging. This is a clear example of a design trade-off that designers must face when
picking a latching and clocking scheme.
The next section discusses how a latch-based design using complementary clock phases can be further
transformed into a edge-triggered-based design.
Edge-Triggered, Flip-Flop-Based Design
The major drawback of a single-phase latch based design is min-timing. The introduction of dual-phaselatch-based
designs greatly reduces the risk of min-timing failure; however, from a physical implementation
perspective, the insertion of a latch in the middle of a pipeline stage is not free of cost. Each
CK