U. Glaeser

14.2 Power Estimation
As we saw in the last section, power dissipation in VLSI circuits is a major concern in the electronics
industry. The rapid increase in the complexity and the decrease in design time have resulted in the need
for efficient power estimation tools that can help in making important design decisions early in the design
process. To accomplish this objective, the estimation tools must operate with a design description at the
higher levels of abstraction; however, trade-offs exists between accuracy and speed in power estimation
at various levels of a design hierarchy. In this section, an overview of the different power estimation tools
and techniques are covered.
Need for Power Estimation Tools
Low-power design requires good power analysis tools to evaluate the alternate choices in design. Consider
modern high-performance CPUs, large portions of which are typically custom designed. These designs
involve manual tweaking of transistors to upsize drivers in critical paths. If too many transistors are
upsized, certain designs can lie on the steep part of a circuit’s power-delay curve. The choice of logic
family used, e.g., static versus domino logic, can also greatly influence the circuit’s power consumption.
Figure 14.6 illustrates these scenarios for a 32-bit adder. Suppose a designer has the data shown in the
figure at his disposal. Knowledge of where on the power-delay curve the circuit operates can tell the
designer whether he/she can trade a little performance for larger power savings. In this example, a total
of 69% savings can be gained by transistor sizing and using domino instead of static logic. There is a
23% delay penalty. This extra delay penalty may be overcome by upsizing adjacent blocks at a much less
power penalty and ending up with an overall power benefit. Experiments with this methodology have
yielded 10% power savings with no delay increase in real designs. CAD tools that enable this kind of
logic and circuit design exploration for custom circuits can thus have a significant impact at the fullchip
level. Specifically, power analysis tools enable designers to:
1. Verify whether the power budgets are met by different parts of the design and identify the parts
that do not satisfy the power requirements
2. Evaluate the effect of various optimizations and design modifications on power
A typical design flow has four steps. It starts with very high-level description of a design, called HLM
(high-level modeling) or architectural description. Then the HLM is converted into RTL (register transfer
level), and then RTL is synthesized into a gate level design. Finally, gates are replaced by transistors/layout
FIGURE 14.6 Power-delay curves for two different 32-bit adders.
© 2002 by CRC Press LLC
Power
69%
CMOS
Domino
PD curve for Domino
23%
Current Domino
design
Delay
Limit of CMOS design
Current CMOS
design
PD curve for CMOS