U. Glaeser

TABLE 2.7 Performance of sub-1 V MTCMOS/SIMOX-LSI
LSIs Gate Length Source Voltage
threshold voltages—some have a high V th and others a low one. High-speed operation at low supply
voltages can be achieved by using low V th MOSFETs to construct the logic circuits and blocking the
standby leak current that arises in these logic circuits because of the low V th with power switch transistors
constructed of high V th MOSFETs, making it possible to apply these circuits to battery-driven devices
such as wearable information equipment. A DSP (1.2 V, 20 MHz operation) that employs this technology
has already been introduced in a wristwatch personal handy-phone system terminal, contributing to
lower power consumption in audio signal processing [26].
Using FD SOI devices to construct the MTCMOS circuits even further improves the operation speed
under low-voltage conditions [27]. By combining 0.25–0.18 µm gate FD SOI devices and MTCMOS
circuit technology, it is fully possible to implement a digital signal processing chip for a wearable terminal
that operates at high speeds (100 MHz or higher) at 1 V. The performance levels of various prototype
MTCMOS/SIMOX chips are listed in Table 2.7.
Analog Circuits
Problems associated with low-voltage operations
We will begin with the problems concerning the low-voltage driving of amplifiers and analog switches,
which are the basic circuits of analog circuits. The trends in supply voltage (V dd), cut-off frequency (fT),
and analog signal frequency (fsig) that accompany the increasingly finer scale of bulk-Si CMOS devices
are shown in Fig. 2.97. These parameters are drawn from the trends related to mixed-signal LSI circuits
predicted in the 1999 SIA Roadmap [2]. The supply voltage exhibits a trend toward portable devices.
The reduction in signal amplitude that comes with a lower supply voltage is a critical concern for analog
circuits. The lower signal amplitude causes a degradation of the signal-to-noise (S/N) ratio. Because the
linear output range of the basic amplifier used in analog circuits extends from ground to V dd minus about
twice the V th of the transistor. So, lowering of the V th is essential to realizing a 1-V, operation-mixed signal
LSI circuit.
On the other hand, lowering the V th increases the leak current of the analog switch, reduces the
accuracy of the A/D converter, generates an offset voltage in the sample-hold circuit, creates highfrequency
distortion in switch-type mixer circuits, etc. The relation between the transistor V th and the
voltage variation caused by the analog switch leak current and the relation between the transistor V th
and the analog signal amplitude, when V dd is 1 V, are shown in Fig. 2.98. The voltage variation values
in that figure are the values calculated for an SC integrator (10 MHz sampling frequency and 1 pF
integral capacitance) that uses analog switches. For a V th of 200 mV, the voltage variation in the
subthreshold characteristics (S = 85–90 mV/dec) of bulk Si devices and PD SOI devices is 3 mV or
more, and 8-bit accuracy in an A/D converter cannot be guaranteed with a 1-V amplitude input signal.
FD SOI devices, on the other hand, have a steep subthreshold characteristic and the leak current can
be suppressed, so the voltage variation is 1 mV or less. This feature can improve the relations among
the S/N ratio, signal band, voltage variation due to leak current, etc., which are trade-offs in analog
circuit design.
© 2002 by CRC Press LLC
V th
Configuration
Operating
Frequency
Power
Consumption
16-bit ALU 8 K 0.5 V Dual 40 MHz 0.35 mW
Communication 8 K 0.5 V Dual 100 MHz 1.45 mW
Coding LSI 30 K 0.5 V Dual 18 MHz 2 mW
8-bit CPU 53 K 0.5 V Dual 30 MHz 5 mW
Communication LSI 200 K 1 V Dual 60 MHz 150 mW
16-bit adder 2 K 0.5 V Triple 50 MHz 0.16 mW
Communication LSI 8 K 0.5 V Triple 100 MHz 1.65 mW
54-bit adder 26 K 0.5 V Triple 30 MHz 3 mW