U. Glaeser

Gate-Induced Drain Leakage (I 4)
GIDL current arises in the high electric field under the gate/drain overlap region causing deep depletion
[7] and effectively thins out the depletion width of drain to well p-n junction. The high electric field
between gate and drain (a negative V G and high positive V D bias for NMOS transistor) generates carriers
into the substrate and drain from direct band-to-band tunneling, trap-assisted tunneling, or a combination
of thermal emission and tunneling. It is localized along the channel width between the gate
and drain. GIDL is at times referred to as surface band-to-band tunneling leakage. GIDL current is
seen as the “hook” in the waveform of Fig. 16.3 that shows increasing current for negative values of
V G (gate bias dependent specially observed at high V D curves). Thinner T ox and higher V DD (higher
potential between gate and drain) enhance the electric field dependent GIDL. The impact of drain
(and well) doping on GIDL is rather complicated. At low drain doping values, we do not have high
electric field for tunneling to occur. For very high drain doping, the depletion volume for tunneling
will be limited. Hence, GIDL is worse for drain doping values in between the above extremes. Very
high and abrupt drain doping is preferred for minimizing GIDL as it provides lower series resistance
required for high transistor drive current. GIDL is a major obstacle in I OFF reduction. As it was discussed,
a junction related bulk band-to-band tunneling component in I 1 may also contribute to GIDL current,
but this current will not be gate bias dependent. It will only increase baseline value of I 4 current
component.
We isolated I GIDL by measuring source current log(I s) versus V G. It is seen as the dotted line extension
of the V D = 4.0 V curve in Fig. 16.3. I GIDL is removed since it uses the drain and substrate (well) terminals,
not the source terminal. The GIDL contribution to I OFF is small at 2.7 V, but as the drain voltage rises to
4.0 V (close to burn-in voltage), the off-state current on the V D = 4.0 V curve increases from 6 nA (at
the dotted line intersection with V G = 0 V) to 42 nA, for a GIDL of 36 nA. The pure weak inversion and
reverse bias p-n junction current of 99 pA is approximated from the V D = 0.1 V curve.
Punchthrough (I 5)
Punchthrough occurs when the drain and source depletion regions approach each other and electrically
“touch” deep in the channel. Punchthrough is a space-charge condition that allows channel current to
exist deep in the subgate region causing the gate to lose control of the subgate channel region. Punchthrough
current varies quadratically with drain voltage and S t increases reflecting the increase in drain
leakage [8, p. 134]. Punchthrough is regarded as a subsurface version of DIBL.
Narrow Width Effect (I 6)
Transistor V T in nontrench isolated technologies increases for geometric gate widths in the order of ≤0.5 µm.
An opposite and more complex effect is seen for trench isolated technologies that show decrease in V T
for effective channel widths on the order of W ≤ 0.5 µm [9]. No narrow width effect was observed in
our transistor sizes with W >> 0.5 µm.
Gate Oxide Tunneling (I 7)
Gate oxide tunneling current I ox, which is a function of electric field (E ox), can cause direct tunneling
through the gate or Fowler–Nordheim (FN) tunneling through the oxide bands [Eq. (16.1)] [8]. FN
tunneling typically lies at a higher field strength than found at product use conditions and will probably
remain so. FN tunneling has a constant slope for E ox > 6.5 MV/cm (Fig. 16.5). Figure 16.5 shows significant
direct oxide tunneling at lower E ox for thin oxides.
© 2002 by CRC Press LLC
IOX =
A⋅ EOX ⋅ e
2
B
– -------
Eox (16.2)