U. Glaeser

FIGURE 31.20 Scaling of link performance with process technology.
at the input of the phase detector can compensate for the setup delay. The most accurate compensation
is to use a replica of the receiver as the phase detector since the setup time is inherent to the receiver;
however, this poses challenge because a receiver does not give phase information proportional to the
phase difference. The output only indicates that the loop clock is either earlier or later than an reference
clock transition. An oscillator-based loop is not stable with this type of bang-bang control so only DLLs
can be built. In order to also lock to the input frequency, a clever design uses a dual-loop architecture
that locks to the input frequency using a core loop [21,27,44]. Coarsely-spaced clock phases from the
core loop are interpolated 25 to generate a clock phase that can be finely controlled. This loop clock is
locked to the input phase using a receiver replica phase detector. Using these techniques, phase offsets
can be smaller than 2% of the bit time.
31.5 Conclusion
This chapter has described the design goals and challenges for high-performance I/O. Performance using
2:1 multiplexing of greater than 5 Gb/s has been demonstrated using a 0.18-µm CMOS technology
[16,18,40]. Higher bit-rates have been shown using higher degree of multiplexing and demultiplexing.
Because transistor speeds will scale with technology, link speeds are expected to scale as well. Unfortunately,
noise coupling due to parasitic capacitances and inductances increases with frequency requiring designs
to be even more robust to noise. Designs employ many of the noise reductions techniques described in
this chapter and have continued to scale. Figure 31.20 illustrates the scaling so far. Future designs will need
to improve these noise reducing and filtering techniques. Furthermore, wire bandwidth does not scale
with technology scaling so the compensating for the low-pass filtering will be even more important.
Methods are being researched that can squeeze more bits into existing bandwidth. Given an SNR,
Shannon’s limit shows the maximum channel capacity to be Capacity/f bw = log(1 + SNR). Researchers
are beginning to show that multilevel (4 + PAM) can be encoded in each bit period at the gigabits per
second broadband data rate [10,13]. This and many techniques [37] that have been demonstrated in
phone modems [4,23] can dramatically increase capacity to 10 bits/Hz in extremely noisy conditions,
but all require accurate A/D and D/A converters. Research has shown that they are feasible but require
extremely accurate timing. Low-jitter PLLs that lock accurately to the data phase are critical in maintaining
the resolution at the gigahertz sampling rates.
25 Interpolation takes two clock phases and performs a weighted average to generate an intermediate clock phase
[32,52].
© 2002 by CRC Press LLC
bit time (psec)
2000
1500
1000
[14] [29]
[49]
[11]∗
[9]∗
[21]
500
1 FO-4
0
0.0
[16,18,30]]
[40]
[52]
[52]
0.2 0.4 0.6 0.8
[52]
1.0 1.2
feature size (µm)
[2]
3 FO-4