U. Glaeser

Modern Designs
Most high-performance processors now incorporate some form of superscalar processing. Even many
simple processors can decode and execute one integer instruction along with one floating-point instruction
per cycle. We briefly survey three representative processors in the following subsections. Other notable
superscalar designs include the Compaq Alpha 21264, HP 8000, and MIPS R10000. It should be noted
that designers of IBM mainframes developed a superscalar implementation, the IBM ES/9000 Model
520, in 1992, but more recent implementations have reverted to scalar pipelines.
UltraSPARC, 1995, [8]
The UltraSPARC is an example of an in-order superscalar processor. It provides four-way instruction
issue to nine functional units. The design team extensively simulated many alternatives and concluded
that an out-of-order approach would have required a 20% penalty in clock cycle time and increased the
time to market by up to half a year. The final design involves a nine-stage pipeline. This includes a decoupled
front-end pipeline (fetch and decode stages) that performs branch prediction and places decoded instructions
in a 12-entry buffer. A grouping stage then selects up to four instructions in-order from the buffer
to be issued in the next cycle. Precise exceptions are provided by padding out most function unit pipelines
to four stages each (i.e., the required length for the floating-point pipelines) so that most fourinstruction
groups complete in-order. The final two stages resolve any exceptions in the groups and write
back the results.
PowerPC 750, 1997, [9]
The PowerPC 750 is an example of an out-of-order processor with distributed reservation stations and
a reorder buffer (called the completion buffer in the 750). The 750 has six function units, including two
integer units. Each unit has one reservation station, except the load/store unit, which has two. Instructions
can issue, when ready, from these reservation stations. (This limited form of out-of-order execution is
sometimes called “function unit slip.”) The 750 also includes six rename registers for renaming the 32
integer registers and six rename registers for renaming the 32 floating-point registers.
The overall pipeline works as follows. A decoding stage is not needed since instructions are predecoded
into a wider representation as they are filled into the instruction cache. Up to four instructions are fetched
per cycle into a six-entry instruction buffer. Logic associated with the instruction buffer removes any
nops or predict-untaken branches and overwrites predict-taken branches with target-path instructions
so that no instruction buffer entries are required for nops or branches. (However, predicted branches are
kept in the branch unit until resolution to provide for misprediction recovery.) Up to two instructions
can be dispatched per cycle to the reservation stations and can be allocated entries in the six-entry
completion buffer. The integer units require a single cycle for execution, while the load/store unit and
the floating-point unit require two and three cycles, respectively. After execution, results are placed into
the assigned entries in the completion buffer. Up to two entries per cycle can be written back from the
completion buffer to the register files.
Pentium 4, 2000, [5]
The Pentium 4 is the most recent 32-bit processor from Intel and is an example of a very aggressive outof-order
processor with a centralized instruction window and a reorder buffer. The original Pentium
combines two integer pipelines, each similar in design to the pipeline of the 486, and can thus decode
and execute up to two instructions in-order per cycle. Intel then developed the P6 core microarchitecture,
which serves as the basis for the Pentium Pro, Pentium II, and Pentium III. After branch prediction and
instruction fetch, the P6 core decodes up to three variable-length Intel IA-32 instructions each cycle and
translates them into up to six fixed-length uops (microoperations). Up to three uops are processed by
register renaming logic each cycle, and these are placed into the 20-entry centralized instruction window
along with being allocated entries in the 40-entry reorder buffer. The window is scanned each cycle in a
pseudo-FIFO manner in an attempt to issue up to four uops. Preference is given to back-to-back uops
to reduce the amount of operand forwarding among the execution units. The actual scanning and issue
requires two cycles, while most instructions require single-cycle execution. At maximum, the reorder
© 2002 by CRC Press LLC