U. Glaeser

left around 30% of complex gates. The CPU time spent on global path tracing techniques of the FANalgorithm
was immensely larger.
In local mode, CTEST can also handle circuits including bi-directional transistors [34] and small
sequential circuits like flip-flops and latches.
Modified FAN Approach
MILEF is based on extensions of the de-facto standard FAN [1] for the test generation at the gate-level.
The original FAN-algorithm is not able to generate test patterns for circuits, including switch-level
macros, because FAN is exclusively based on controlling and noncontrolling values of the gates, which
in general do not exist for switch-level macros. Consequently, the modified FAN in MILEF also handles
Boolean functions of switch-level macros, i.e., multiple cubes [3]. Thus the main FAN functions such as
implication, unique sensitization, and multiple backtrace are modified to handle switch-level macros.
The modified FAN approach is described as follows (see also Fig. 45.1):
As a preprocess of the test generation process, gate-level netlists are analyzed for path reconvergencies.
They have to be identified for the reconvergency analysis described in subsection on “Merging of Test
Pattern Pairs.” Most path reconvergencies in practical circuits are of a local nature, so this procedure is
quite useful. Results are also transferred to the local switch-level test generator for specific macros in order
to obtain globally applicable local test patterns from the beginning (see section “Reconvergency Analysis”).
Furthermore, redundancies discovered during this initial step are included in the formal testability analysis.
The constraint list is used later in conjunction with global implications in the FAN algorithm.
The second preprocessing step for the gate-level test generation is the formal testability analysis. In
particular, the formal controllability and observability analysis guiding the path searching process in FAN
was modified in order to also accommodate switch-level macros. Modified testability measures that can
optionally be used are, for instance, COP [35], LEVEL [36], SCOAP [37], and EXTEST [8]. We got the
best experimental results in MILEF by using COP.
Furthermore, the initial FAN-functions for implication, sensitization, and multibacktrace [1] are
modified for handling switch-level macro cells described by multiple cubs [3]. Information for propagation
over switch-level macros is described in a 9-valued logic, e.g., multiple cubes are used, and the
good and faulty machine are described separately [10].
As MILEF is based on the transition fault model, pattern sequences instead of single vectors are
generated. If possible, pattern pairs are merged into longer sequences to minimize initialization efforts
and to save on the overall test length.
The path searching performed by MILEF differs from approaches known from gate delay fault test
generation in three ways:
• Initialization is excited at a particular gate and test for a particular gate is propagated to primary
outputs. The transition may not be observable directly as a transition at one output, which means
it can also be observable because of a transition at an output in the faulty case. For example, in
Fig. 45.3, the stuck-open fault at the n-transistor with the gate connected to A1
in g1
will cause a
stable 1 at C and thus a rising transition at D while in the “good case” D has a “0” value.
• Hazard analysis concentrates on static hazards that can invalidate the test by switching other paths
or elements to “conducting” (see subsection “Robustness Check for Pattern Pairs”).
• For the generation of only overcurrent-related test vectors in combination with Iddq measurements,
the propagation of faults to primary circuit outputs can be omitted. This results in a simplified
path-tracing process and fewer patterns.
Three phases of test generation are used in MILEF. In the first phase, test patterns are computed for all
easily detectable faults and no backtracking is allowed. No dynamic fault sensitization [2] and no dynamic
learning [4] are used in this step. The user may give a backtrack limit for the second phase in which the
extensions of SOCRATES [2] are used. For redundancy identification and generating test patterns for
hard detectable faults, dynamic learning [4] is used in the third phase of test generation.
© 2002 by CRC Press LLC