U. Glaeser

a small fraction of circuit nodes that are clock powered accounts for most of the power dissipation if
they were powered from a dc supply voltage.
Equation (21.4) also defines the absolute maximum degree to which adiabatic charging can be used
to reduce dissipation. As the clock transition time approaches infinity, the first term of Eq. (21.4)
approaches zero and the dissipation is solely determined by the second term.
© 2002 by CRC Press LLC
R
i
, the effective resistance
of the charge-transfer path, is the difficult parameter to quantify. It depends upon the circuit topology
of the E-R latch as shown in detail in section 21.4.
21.3 Clock Driver
Two known circuit types can be used as clock drivers in a clock-powered system: resonant [3,17] and
stepwise [8]. For the purposes of this text, only resonant drivers will be presented due to their superior
energy efficiency.
A simple resonant clock driver can be built from an LRC circuit that generates sinusoidal pulses. Such
a circuit can be formed with two nFETs ( M1
and M2)
and an inductor ( L)
(Fig. 21.2). The capacitor Cϕ
represents the clock load. The resistance of the clock line is assumed negligible compared to the onresistance
of M1.
Two nonadiabatically-switched control signals drive M1
and M2.
The circuit generates
sinusoidal pulses if operated as follows. Assume that ϕ is at 0 V, i.e., Cϕ
is discharged and that both M1
and M2
are off. Then M1
is turned on and M1,
L,
and Cϕ
form an LRC circuit that produces a sinusoidal
1/
2
pulse with width 2π(
LCϕ)
and amplitude approximately 2⋅Vdc. M1 should be turned off exactly at the
end of the pulse. Then M2 is turned on and fully discharges ϕ. Two such circuits can be synchronized to
generate two nonoverlapping phases. If Ts is the pulse switching time, it can be shown [3] that the energy
– 1/2
– 1
for switching ϕ scales as Ts instead of Ts solely because M1 and M2 are controlled by nonadiabatically-
switched signals.
The LRC clock driver can be further simplified by eliminating the series nFET M1 and using a single
signal to control the pull-down nFET (Fig. 21.3). When the nFET is on, a current is built in the inductor
while ϕ is clamped at 0 V. When the nFET is turned off, the current flows to the load Cϕ, generating a
– 1/2
sinusoidal pulse. The energy dissipation for switching Cϕ still scales as Ts because the nFET is driven
by a nonadiabatically-switched signal; however, two such circuits can combine as shown in Fig. 21.4
to form an all-resonant configuration [18] that generates two almost nonoverlapping clock phases
– 1
(Fig. 21.5). The energy for switching the clock loads in the all-resonant configuration scales as Ts since
the control signals are adiabatically switched.
FIGURE 21.2 A simple LRC resonant clock driver ([18] © 1996 IEEE).
FIGURE 21.3 A single-phase resonant clock driver ([28] © 1997 IEEE).
V dc
V dc
in
M 1
L
ϕ
L
C ϕ
in
ϕ
M 2
ϕ
Cϕ