U. Glaeser

U. Glaeser
Halstenbach ACT GmbH
Z. Stamenković
∨
University of Ni s
H. T. Vierhaus
Bradenburgische Technische
Universitat
45.1 Introduction
© 2002 by CRC Press LLC
45
Testing of Synchronous
Sequential Digital
Circuits
45.1 Introduction
45.2 Mixed-Level Test Generation
Basic Concepts • Switch-Level Test Generation
• Modified FAN Approach • Robustness Check
for Pattern Pairs • Inter-Level Communications
• Reconvergency Analysis • Merging of Test Pattern
Pairs • Comparative Results
45.3 The Fogbuster Algorithm for Synchronous
Circuits
Circuits • General Approach in Comparison with
Other Algorithms • Test Generation Technique • Fault
Propagation and Propagation Justification • The
Over Specification Problem in Sequential Test
Generation • Detection of State Repetitions in Test
Generation • Use of Global Set and Reset Signals
in ATPG • Experimental Results
45.4 Summary
Automatic test generation for combinational logic based on the FAN algorithm [1,2], relying on the Dalgorithm
[3] has reached a high level of maturity. FAN has also been modified for test generation in
synchronous sequential circuits [4,5]. Because the shortcomings of the static stuck-at fault model in the
detection of opens, dynamic faults, and bridging faults [6,7], became evident, interest has focused on
refined fault modeling either using switch-level structures or dynamic gate-level fault models.
The authors have shown [8–10] that the potential fault coverage by stuck-at-based test patterns for
transistor faults is potentially as high as 80% or above if the circuit consists of simple 2- and 3-input fully
complementary static CMOS gate primitives (AND, NAND, OR, NOR) only, but may drop to 60% or
below if complex gates and pass-transistor networks are used. The first solution to this problem is switchlevel
test generation [11], which is inherently slower than gate-level test generation. The need for test
generation based on real transistor structures is also demonstrated by industrial work [12], which reported
the first mixed-level test generation approach.
Advanced work in this area was reported more recently in [13–15]. The main problem associated with
such methods is the adequate fault modeling based on the transistor circuitry for structures other than
primitive logic gates. Cox and Rajski [16] have shown that also using a transition fault model in ATPG,
transistor faults in fully complementary CMOS complex gates can be covered by gate-level networks.