U. Glaeser

FIGURE 5.15 Organizing the PEs of a multithreaded processor as a circular queue.
parallel on multiple PEs instead of time-sharing a single PE. As we look into the future, and the prospect
of a billion transistors on a single chip, it seems inevitable that microprocessors will have multiple PEs.
PE Organization
The next issue of importance in a multithreaded processor is the organization of the PEs. This issue is
strongly tied to the PE interconnect used. Most of the sequential threads model based processors organize
the PEs as a circular queue, as shown in Fig. 5.15. The circular queue imposes a sequential order among
the PEs, with the head pointer indicating the oldest active PE. When the tail PE is idle, a thread allocation
unit (TAU) invokes the next thread (as per the sequential thread ordering) on the tail PE and advances
the tail pointer. Completed threads are retired from the head of the PE queue, enforcing the required
sequential ordering. Although this PE organization is tailored for sequential threads (from a sequential
program), this multithreaded hardware can also execute multiple threads from different processes, if
required.
An important issue that needs to be considered when organizing the PEs as a circular queue is load
balancing. If some PEs have long threads assigned to them, and the rest have short ones, only modest
performance will be obtained. If threads are not close to the same size, a short thread may complete soon
and perform no useful computation while it waits for longer predecessor threads to retire. To get good
performance, threads should be of uniform length. 1 One option to deal with load balancing, albeit with
additional hardware complexity, is to let each physical PE have multiple virtual PEs and assign a thread
to each of the virtual PEs.
Inter-PE Register Communication and Synchronization
As discussed earlier, a few multithreading approaches have a shared register space for all threads, and the
rest do not. When threads share a common register space, the thread sequencing model has always been
the sequential threads model. Because the semantics of this model are in line with sequential control
flow, synchronization happens automatically, once inter-PE register communication is handled properly.
Register File Implementation
When threads do not share a common register space, it is straightforward to implement the register file
(RF)—each PE can have its own register file, thereby providing fast register access. When threads share
1 The actual, more stringent, requirement is that the thread execution times should be matched across all PEs. This
is a more difficult problem, because it depends on intra- and inter-PE data dependences as well.
© 2002 by CRC Press LLC
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