U. Glaeser

FIGURE 9.8 Two’s complement subtracter.
Fixed-Point Subtraction
As noted in previous subsection, subtraction of two’s complement numbers is accomplished by adding
the minuend to the inverted bits of the subtrahend and adding a one at the least significant position.
Figure 9.8 shows a two’s complement subtracter which computes A − B. The inverters complement the
bits of B; formation of the two’s complement is completed by setting the carry into the least significant
adder stage to a ONE.
Fixed-Point Multiplication
Multiplication is generally implemented either via a sequence of addition, subtraction, and shift operations
or with direct logic implementations.
Sequential Booth Multiplier
The Booth algorithm [8] is widely used for two’s complement multiplication, since it is easy to implement.
Earlier two’s complement multipliers (e.g., [9]) required data dependent correction cycles if either operand
is negative. To multiply A B, the product, P, is initially set to ZERO. Then, the bits of the multiplier,
A, are examined in pairs of adjacent bits starting with the least significant bit (i.e., a 0a −1) and assuming
a −1 = 0:
• If ai = ai−1, P = P/2
• If ai = 0 and ai−1 = 1, P = (P + B)/2
• If ai = 1 and ai−1 = 0, P = (P – B)/2
The division by 2 is not performed on the last stage (i.e., when i = n − 1). All of the divide-by-two
operations are simple arithmetic right shifts (i.e., the word is shifted right one position and the old sign
bit is repeated for the new sign bit), and overflows in the addition process are ignored. The algorithm is
illustrated in Fig. 9.9, which shows the formation of products for all combinations of ±5/8 times ±3/4
for 4-bit operands. The sequential Booth multiplier requires n cycles to form the product of a pair of
n-bit numbers, where each cycle consists of an n-bit addition and a shift, an n-bit subtraction and a shift,
or a shift without any other arithmetic operation.
Sequential Modified Booth Multiplier
The radix-4 modified Booth multiplier described by MacSorley [2] uses n/2 cycles where each cycle
examines three adjacent bits, adds or subtracts 0, B, or 2B and shifts two bits to the right. Table 9.3 shows
the operations as a function of the three bits a i+1, a i, and a i−1. The radix-4 modified Booth multiplier
takes half the number of cycles as the “standard” Booth multiplier, although the operations performed
during a cycle are slightly more complex (since it is necessary to select one of five possible addends instead
of one of three). Extensions to higher radices that examine more than three bits [10] are possible, but
generally not attractive because the addition/subtraction operations involve non-power of two multiples
(such as 3, 5, etc.) of B, which raises the complexity.
© 2002 by CRC Press LLC
c n
a n-1 b n-1 a 2 b 2 a 1 b 1 a 0 b 0
s n-1
s 2
n-Bit Adder
s 1
s 0
c 0
1