U. Glaeser

FIGURE 5.4
also available and are used for applications requiring large data sets. Each CPU processing core consists
of several arithmetic and logic units (ALU), multi-ported register files, floating point multipliers, and
branch execution units. Most widely used CPU architecture can execute instructions out of order (OOO)
and several operations at a time (super scalar).
Server applications operate on many instruction and data sets. During program execution, the same
instruction and data elements may be repeatedly used. High-performance CPU execution rate requires
high instruction and data bandwidth. Caches are used to store and operate on the most frequently used
instruction and data as well as provide high bandwidth for fast execution. A high-performance server
CPU contains several levels of hardware caches. Each cache may consist of separate instruction and data
caches or an integrated instruction and data cache. Caches are numbered in increasing order, starting
from one from the processing core toward system memory. The size of each cache in the order of increasing
number is several times that of a lower level cache. Current server microprocessors use L3 or L4 caches
to achieve highest level of performance. Cache size, associativity, line size, and replacement policy are
determined by the characteristics of the desired applications running on the server using performance
simulation models. Caches costs are determined by the state-of-the-art VLSI processing technology,
implementation, and power dissipation considerations.
The number of CPUs used in a server is determined by the server performance requirement and design
limitations. Most server designs contain several sockets for optional future CPU enhancement. Multiple
CPUs provide more computing performance. Architecture and design of high performance MP architectures
is still an active area of research.
Cost considerations also demand sharing of expensive resources such as system memory or peripheral
storage devices. High-performance arbitrated access to common system resources by all CPUs is another
topic of current research in server design.
System Memory
One of the critical subsystems in a server is the system memory. System memory consists of several banks
of dynamic random access memory (DRAM) modules. The larger the number of independent memory
banks, the larger is the total bandwidth available to system devices requesting memory access (such as
CPUs and peripheral devices). There are a variety of DRAM memory configurations such as single in-line
memory module (SIMM) or dual in-line memory module (DIMM). Current servers can have several
gigabytes of system memory.
Due to need for improved reliability and robustness, server system memory use fault tolerance features
such as ECC. Errors can happen for a variety of reasons such as DRAM memory soft error rate (SER)
or errors in transmission signaling among various chips. Another robustness measure is the number of
error bits than can be detected and corrected. Low-end servers use single error correct double error detect
(SECDED). Another robustness feature is chipkill. Chipkill enables isolation and correction of multi-bit
faults such as failure of a single memory chip.
Finally, because server system memory may be large, auto-initialization of memory values to known
values such as during power up may be required. Other robustness features include memory mirroring,
© 2002 by CRC Press LLC
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