U. Glaeser

architecture, the implementation, and the compilers be specifically designed to support the packaging
of multiple independent operations into long instruction words.
Proponents of the VLIW approach rightly contend that VLIW design reduces the control complexity
within a processor; however, the corresponding drawbacks are a loss of program portability at the binary
level and a lack of flexibility. With regard to portability, the control logic added by a superscalar processor
is used to dynamically determine opportunities for parallel execution within a conventional instruction
stream. Thus, superscalar processors dynamically schedule parallel execution of the instructions of existing
executable program files, whereas recompilation into a static representation of parallel execution is a
requirement for programs to run on VLIW processors. With regard to flexibility, superscalar processors
can easily respond to dynamic events, such as cache misses. Dynamic events present a difficulty for VLIW
designs. For example, early VLIW designs avoided data caches so that memory access time would be a
known quantity for use in compiler scheduling.
The recent introduction of EPIC (Explicitly Parallel Instruction Computing) architectures, such as the
IA-64 architecture of Intel and Hewlett-Packard, is an attempt to gain the best of both approaches. Explicit
dependence information is incorporated into the instruction formats to reduce the control logic complexity,
and some scheduling of dynamic behavior is incorporated to provide flexibility.
Instruction-Level Parallelism
Superscalar processors attempt to identify and exploit parallelism in the instruction stream. That is,
instructions that are independent should be executed in parallel. We briefly review the concept of dependencies.
More details can be found in Mike Johnson’s text on superscalar microprocessor design [1].
Dependencies
Dependencies limit the parallelism between instructions because they must be enforced so that the results
of program execution will be correct. Indeed, much of the control logic in a superscalar processor is
devoted to identifying dependencies, so that execution will produce the same results as if the instruction
stream was being executed on a purely sequential computer. Dependencies can be categorized in three ways.
Data Dependencies
Data dependencies exist between two instructions when the order between the two instructions must be
maintained for execution to be correct. The most obvious data dependency is the true data dependency (or
RAW: read-after-write dependency) in which the result of one instruction is used as an input operand for
the second instruction. To preserve correctness, the first instruction must be executed prior to the second.
The storage that is used first as a result and then as a source can be either a memory location or a CPU register.
Two other cases arise when the second instruction writes to a storage location. An output dependency
(or WAW: write-after-write dependency) occurs when both instructions write to the same storage. To
preserve correctness, the result of the second instruction must be the final value of the storage. An antidependency
(or WAR: write-after-read dependency) occurs when the first instruction reads an input
operand from the storage location that will be written with the result of the second instruction. To preserve
correctness, the first instruction must obtain its input operand before that value is overwritten by a new
value from the second instruction. Both of these cases are called false data dependencies because they arise
from the reuse of storage locations.
Control Dependencies
A control dependency occurs when an instruction depends on a conditional branch instruction. It is not
known whether the instruction is to be executed or not until the branch is resolved. Thus, the branch
must be executed prior to the instruction.
Structural Dependencies
A structural dependency occurs when two instructions need the same resource. If the resource is not
duplicated, the instructions must execute sequentially, one after the other, rather than in parallel. The resource
for which the instructions contend might be an adder, a bus, a register file port, or some other component.
© 2002 by CRC Press LLC