U. Glaeser

greater than one, the system is overdamped as the PLL output initially responds rapidly but then takes
a long time to reach the final phase. The rate of the initial response increases and the rate of the final
response decreases as the damping factor is increased above one.
PLL with Higher-Order Roll-Off
It is very common for an actual PLL implementation to contain an extra capacitor, C2, in shunt with the
loop filter, as shown in Fig. 10.8. This capacitor may have been introduced intentionally for filtering or
may result from parasitic capacitances within the resistor or at the input of the VCO.
Because the charge pump and phase detector are activated once every reference frequency cycle, they
can cause a periodic disturbance on the control voltage node. This disturbance is usually not an issue for
loops with N equal to one because the disturbance will occur in every VCO cycle. However, the disturbance
can cause a constant shift in the duty cycle of the VCO output. When N is greater than one, the disturbance
will occur once every N VCO cycles, which could cause the first one or two of the N cycles to be different
from the others, leading to jitter in the PLL output period. In the frequency domain, this periodic
disturbance will cause sidebands on the fundamental peak of the VCO frequency spaced at intervals of
the reference frequency.
Capacitor C2 will help filter out this reference frequency noise by introducing a pole at ωC. It will
decrease the magnitude of the reference frequency sidebands by the ratio of ω REF/ωC. However, the
introduction of C2 can also cause stability problems for the PLL since it converts the PLL into a thirdorder
system. In addition, C2 makes the analysis of the PLL much more difficult.
The PLL is now characterized by the four loop parameters ω N, ωC, ζ, and N. The damping factor, ζ,
is changed by C2 as follows:
© 2002 by CRC Press LLC
F REF
N
Phase
Detect
FIGURE 10.8 Typical PLL block diagram with C 2 (clock distribution omitted).
U
D
Charge
Pump
ζ = 1�2 ⋅ (1 � N ⋅ I CH ⋅ K V ⋅ R 2 ⋅ C 2 �(C + C 2)) 0.5
The loop bandwidth, ω N, is changed by C 2 through its dependency on ζ. The added pole in the openloop
response is at frequency ω C given by
ω C = (C + C 2) �(R ⋅ C ⋅ C 2)
This pole can reduce the stability of the loop if it is too close to the loop bandwidth frequency. Typically,
it should be set at least a factor of ten above the loop bandwidth so as not to compromise the stability loop.
Because the stability of the loop is now established by both ζ and ω C�ω N, a figure of merit can be
defined that represents the potential stability of the loop as
ζ ⋅ ω C �ω N = (C/C 2 + 1)�2
This definition is useful because it actually defines the maximum possible phase margin given an optimal
choice for the loop gain magnitude.
Consider the normalized loop gain magnitude and phase plots for the PLL with different ratios of C
to C 2 shown in Fig. 10.9. From these plots, it is clear that the added pole at ω C causes the loop gain
magnitude slope to increase to −40 dB per decade and the loop gain phase to “increase” to −180° above
the frequency of the pole. Between the zero at 1/(R ⋅ C) and the pole at ω C there is a region where the
C
R
C2 VCTRL VCO
I CH (A) K V (Hz/V)
F O