U. Glaeser

has become more and more specialized. As a consequence, adaptation of 1T-DRAM technology with
mainstream logic CMOS technology is decreasing with each new generation. Logic CMOS are available
earlier than technologies with embedded 1T-DRAM. 1T-DRAM is also slow for most applications and
has a high standby current. For these and other reasons market for chips with embedded 1T-DRAM has
shrunk and is limited to those markets, which have already adopted the technology. Major foundries
have stopped their embedded 1T-DRAM developments. Another memory cell that has recently received
attention for high density embedded memory uses a real MOS transistor as the storage capacitor,
Fig. 10.77(c). This cell was also used in the first generation stand alone DRAM (up to 16 kbit). This cell
is more compatible with logic process. Thus, availability will be earlier than 1T-DRAM, it is more flexible
and can be used in many applications. This volume leverage helps in yield improvements and support
from logic technology development.
Table 10.9 compares main performance parameters for these three embedded memory solutions. 2T-
DRAM needs continuous refreshing to maintain the stored signal. This is a major contributor to the
high 2T-DRAM standby power. SRAM and 2T-DRAM also differ in the way they scale with technology.
To see this, consider again the Fig. 10.77.
The following equation summarizes the design criteria for a 2T-cell:
© 2002 by CRC Press LLC
Bit
TABLE 10.9 Comparison of Three Memory Cell
Candidates for Embedded Application
1T-DRAM 2T-DRAM SRAM
Area 1 3X 5X
Active power Low Low High
Standby power High High Low
Speed Low Low High
Yield Low Moderate High
WL
Vcc
P1 P2
s1
s2
NP1 NP2
ND1 ND2
Bit#
FIGURE 10.77 Cell circuits considered for embedded memory.
WL WL
∆V + V n = C sV s /2(C s + C BL) (10.25)
where ∆V is the minimum required voltage for reliable sensing (∼100 mV); V n is the total noise due to
different leakage, voltage drop, and charge transfer efficiency; C s is the storage capacitance; C BL is the
total bit line capacitance; and V s is the voltage on the C s when a “1” is stored in the cell, V cc − V tn. Now
the effect of process development on each parameter will be examined. V n includes sub-threshold current,
gate leakage, which is becoming significant in 0.13 µm and beyond, the charge transfer efficiency, and
voltage noises on the voltage supply. All these components degrade from one process generation to
another. V s also scales down with technology improvements. We assume that C s and C BL scale in the same
way. Then for a fixed ∆V, for each new process generation, fewer numbers of cells must be connected to
the bit line. This will decrease memory density and increase power consumption.
For SRAM the following equation may be used to study the effect of technology scaling:
C BL
Bit
NP
CS CBL ∆V = (I sat/C BL)T (10.26)
Bit
(a) (b) (c)
NP
C S