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U. Glaeser

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Communication devices need to be of small size and low power dissipation for portability and need<br />

to be operated at very high speed. Any of these devices, as other digital products, may consist of a single<br />

integrated circuit (IC) or more likely many ICs mounted on a printed circuit broad (PCB). Although<br />

the new technology (small feature size) has resulted in higher speed ICs, the transfer of data from one<br />

IC to another still creates a bottleneck of information. The I/O pads, with their increasing inductance,<br />

cause supply surges that compromise signal integrity. As an alternative to PCB design, another design<br />

approach known as multichip module (MCM) consists of placing more than one chip in the same<br />

package. The connections between modules have a large capacitive load that slows down communication<br />

among all of the modules. In the late 1990s, a new paradigm design called system-on-a-chip (SoC) has<br />

been successfully used to integrate the components of an entire system on one chip. This is in contrast<br />

to the traditional design where the components are implemented in separate ICs and then assembled on<br />

a PCB.<br />

Section 42.3 describes the new design paradigm of a SoC and its beneficial attributes are outlined.<br />

The remainder of the paper concentrates on communication devices and the subsection on “Need for<br />

Communication Systems” emphasizes the need for these systems. Descriptions of communication SoCs<br />

and projections on their characteristics are given in “Communication SoCs.” Latency, an important<br />

attribute, is the subject of “System Latency”; and “Communication MCMs” describes the integration of<br />

these systems with analog parts in MCM.<br />

System-on-a-Chip (SoC)<br />

The shift toward very deep submicron technology has encouraged IC designers to increase the complexity<br />

of their designs to the extent that an entire system is now implemented on a single chip. To increase the<br />

design productivity and decrease time-to-market, reuse of previously designed modules is becoming<br />

common practice in SoC design; however, the reuse approach is not limited to in-house designs. It is<br />

extended to modules that have been designed by others as well. Such modules are referred to as embedded<br />

cores. This design approach has encouraged the founding of several companies that specialize in providing<br />

embedded cores to service multiple customers. It is predicted that in the near future, cores, of which<br />

40% to 60% will be from external sources [Smith 1997], will populate 90% of a chip. Except for a very<br />

few, individual companies do not have the wide range of expertise that can match the spectrum of design<br />

types in demand today.<br />

Core-based design, justified by the need to decrease time-to-market, has created a host of challenging<br />

problems for the design and testing community. First, there are legal issues for the core provider and the<br />

user, regarding the intellectual property (IP). Second, there are problems with integrating and verifying<br />

a mix of proprietary and external cores that are more involved than simply integrating ICs on a PCB.<br />

A typical SoC configuration is shown in Fig. 42.9. It consists of several cores that are also referred to<br />

as modules, blocks, or macros. Often, these terms are used interchangeably. These cores may be DSP, RAM<br />

FIGURE 42.9 A system-on-a-chip (SoC).<br />

© 2002 by CRC Press LLC

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