U. Glaeser

FIGURE 13.4
TABLE 13.1
combinational logic circuits can be evaluated. In the end, final device sizings, placements, wire level
assignments, buffer sizing and placement, and indeed some circuit designs will be adjusted, as the design
becomes fixed. The final process is aided by device tuning, extraction, simulation, and static timing tools.
In high-frequency designs, the accurate analysis of the wiring becomes critical. Because the designer
is only able to reduce to a limited extent the amount of the cycle time, which must be allocated to clock
uncertainty, latching overhead, and the minimum required function (e.g., a 32-bit addition/subtraction
and muxing of a logical result) pressure to minimize time in signal distribution, is intense. To date, the
shortest technology-independent cycle time for a 64-bit processor, 14.5 FO4 inverter delays, has been an
5
IBM research prototype. The cycle time for this design was allocated according to the budget presented
in Table 13.1.
The time available for distribution of results limits the placement of communicating macros. For results,
which must be driven out of a macro through a wire into a remote receiving latch, an inverter was placed
at the macro output to provide gain to drive the wire and another inverter was placed at the input of the
9
latch to isolate the dynamic multiplexor from any noise on the wire. Thus, the distribution wires could
only be at most about 3.5 mm and thus the core of such a short cycle design with full forwarding must
be quite small. For full-cycle latch-to-latch transfers, the wires were limited to about 10 mm. Figure 13.4
presents the floorplan of the processor with a representative full-cycle latch-to-latch transfer path of
6.5 mm from the fixed point instruction register to the floating-point decoder latches. Figure 13.5 presents
a portion of the fixed point data-flow, FXU, with a representative maximum length forwarding wire of
© 2002 by CRC Press LLC
Gigahertz PowerPC Delay Allocation
Function Delay (ps) FO4 Function Delay (ps) FO4
Mux-latch Clk-Q 200 2.9 Mux-latch Clk-Q 200 2.9
Control logic 470 6.8 Datapath logic 610 8.8
Control distribution 140 2.0 Datapath distribution 140 2.0
Control latch setup 140 2.0 Datapath latch setup 0 0
Clock jitter/skew 50 0.7 Clock jitter/skew 50 0.7
A 1 GHz PowerPC processor floorplan with representative global signal.