U. Glaeser

FIGURE 3.14 Power consumption versus operating frequency of CMOS, ECL, and LS-APD-ECL circuits. The
broken lines represent range of toggle frequencies of flip-flop that cannot be reached by the technology.
than 0.5 µm CMOS under 3.3 V at an operating frequency higher than 780 MHz. In case of applications
with higher probability of gate switching or with an advanced bipolar technology, the crossing frequency
can further be reduced.
3.2 Low-Voltage ECL Circuits
Demand for low-power dissipation has motivated scaling of a supply voltage of digital circuits in many
electronic systems. Reducing the supply voltage of ECL circuits is becoming important not only to reduce
the power dissipation but also to have ECL and CMOS circuits work and interface together, under a
single power supply on a board or on a chip.
Gate stacking in ECL is effective in reducing the power dissipation because complex logic can be
implemented in a single gate with fewer current sources. This, however, brings difficulty in reducing the
supply voltage. Various design techniques for low-voltage ECL have been reported before [9,10], but
none of them allows a use of stacked differential pairs in three levels.
In conventional ECL circuits, input signals to the stacked differential pairs are shifted down by the
emitter-follower circuit to keep all the bipolar transistors out of the saturation region. V IH of the differential
pairs in the nth level from the top is −n · V BE, where V BE is the base-emitter voltage of a bipolar
transistor in the forward-active region. As illustrated in Fig. 3.15, the minimum operating power supply
voltage (minimum |V EE|) of a three-level series gating ECL circuit is 4V BE + V CS, where V CS is the voltage
drop across a tail current source. This implies that scaling V BE is the most effective means of reducing
the minimum |V EE|, but, in practice, V BE does not scale linearly with technology and has remained
constant. For V BE = 0.9 V and V CS = 0.4 V, the minimum |V EE| is 4.0 V. On the other hand, the collectoremitter
voltage (V CE) of the bipolar transistors is 2V BE − V S (=1.5 V) in the top level and V BE (= 0.9 V)
in the second and the third levels, where V S is the signal voltage swing. V CE can be reduced to 0.4 V
without having a transistor enter the saturation region. This V CE voltage headroom comes from the
emitter follower circuit, shifting the signal levels down by V BE.
Figure 3.16 illustrates a voltage level of signals in three-level series gating in a low-voltage ECL (LV-ECL)
circuit [11]. In the LV-ECL circuit, the input signals to the top and the second levels are shifted up by
current mode logic (CML) gates, and the input signals to the third level are directly provided. By adjusting
the amount of the level shifting for the second level by a resistor R S, V CE of the bipolar transistors is set to
© 2002 by CRC Press LLC