U. Glaeser

advantage of this circuit, compared to a circuit with positive feedback, is that it always resolves to right
direction regardless of the initial amount of differential signals at the inputs. Thus it is not sensitive to
the minimum delay of SenSel signal to word line. However, this circuit has many disadvantages. It is
slow and consumes more power. The gain and speed of the circuit is very sensitive to the pre-charge
value of the bit line. Because of the diode connected transistor in the circuit it is not suitable for low
voltage operation and has structural offset. For these reasons the differential sense amplifier with positive
feedback circuit, Fig. 10.86(b), is used in many designs.
This circuit is fast and consumes less power. The only disadvantage of this circuit is that it may latch
in a wrong state. To avoid this, the SenSel signal must be activated after sufficient different voltage is
developed on bit lines to overcome all worst-case offsets of the circuit. To calculate the worst-case offset,
the schematic model in Fig. 10.81 can be used. ∆L and ∆V t are smaller for sense amplifiers because bigger
devices are used here. To reduce the offset, transistors used in the circuit must have at least 10–20%
longer than the minimum length in the technology.
After sufficient differential voltage is developed between V 1 and V 2, the SenSel signal is activated.
Initially, only two input N transistors, N 1 and N 2, are in saturation and two loading P transistors are off.
This is a favorable case because N transistors normally have better matching characteristics than P
transistors. Two cross-coupled N transistors increase the differential voltages further. Both V 1 and V 2
drop below pre-charge V cc voltage. When V 1 or V 2 are below V cc – V tp, the P transistors further increase
the positive feedback and restore a full V cc on the side that is supposed to be a logic “1”. To make the
initial part of the operation longer, one may use a dual slope scheme or/and clock the V cc connection,
Fig. 10.86(c). In the dual slope scheme first the weaker tail transistor is activated. This will cause the V 1
and V 2 to sink slowly. After a short delay the strong tail transistor is turned on by SenSel. In the clocked
V cc connection the Φ L is delayed with respect to SenSel. In some design the Bit and Bit# are not
disconnected from the sense amplifier during sensing. This results in slower response and increased
power consumption. Bit and Bit# can be disconnected by a column select transistors to increase speed
and reduce power consumption.
Memory Array
Now that main circuits comprising a column are presented, we can construct an array of columns. The
goal is to organize n × n cells in such a way to meet the required access time, power budget, and higharea
efficiency. In a flat organization, Fig. 10.87(a), all the cells are included in a single array. This
architecture has many disadvantages for large memories. The main contributor to the power consumption
FIGURE 10.87 Memory organizations: (a) flat, (b) hierarchical, and (c) a hierarchical circuit solution.
© 2002 by CRC Press LLC
Row decoder
Global address
n × n
Cells
Column decoder
Global decoder
Local decoder
LWL
Pre-decoded
1:4
GWL
GWL
(a) (b)
Global decoder Local decoder
(C)
Local decoder
Block select
LWL