U. Glaeser

FIGURE 10.2 Typical DLL block diagram (clock distribution omitted).
FIGURE 10.3 Typical PLL block diagram (clock distribution omitted).
that integrate the phase error in the loop filter using charge pumps [3]. Charge pump PLLs have the
property that in the locked state, the detected phase error is ideally zero.
In general, PLLs can control their output phases directly by delaying the reference signal or indirectly
by changing the output frequency. The first is commonly referred to as a delay-locked loop (DLL) since
it actually locks the delay between the reference input and the feedback input to some fraction of the
reference input period. The second is referred to as a VCO-based PLL or simply as a PLL since it controls
the frequency of a voltage-controlled oscillator (VCO) generating the output such that the feedback input
is in phase with the reference input.
Figure 10.2 shows the general structure of a DLL. It is composed of a phase detector, charge pump,
loop filter, and voltage-controlled delay line (VCDL). The negative feedback in the loop adjusts the delay
through the VCDL by integrating the phase error that results between the periodic reference and delay
line output. When in lock, the VCDL delays the reference input by a fixed amount to form the output
such that the phase detector detects no phase error between the reference and feedback inputs. The clock
distribution network, although not shown in the figure, is between the DLL output and the feedback
input. Functionally, it can be considered as part of the VCDL.
Figure 10.3 shows the general structure of a PLL. It is composed of a phase detector, charge pump,
loop filter, and VCO. Two key differences from the DLL are that the PLL contains a VCO instead of a
VCDL and, as will be discussed below, requires a resistor in the loop for stability. The negative feedback
in the loop adjusts the VCO output frequency by integrating the phase error that results between the
periodic reference input and the divided VCO output. When in lock, the VCO generates an output
frequency and phase such that the phase detector detects no phase error between the reference and feedback
inputs. With no phase error between the reference and feedback inputs, the inputs must also be at the
same frequency. If a frequency divider, which divides by N, is inserted between the PLL output and feedback
input, the PLL output will be N times higher in frequency than the reference and feedback inputs, thus
allowing the PLL to perform frequency multiplication.
The difference in loop structure between a DLL and a PLL gives rise to different properties and
operating characteristics. DLLs tend to have short locking times and relatively low tracking jitter, but
generally do not support frequency multiplication or duty cycle correction, have limited delay ranges,
and require special lock reset functions. PLLs have unlimited phase ranges, support frequency multiplication
and duty cycle correction, do not require special lock reset functions, but usually have longer lock
times and higher tracking jitter. DLLs are less complex than PLLs from a loop architecture perspective,
but are generally more complex from a design and system integration perspective.
© 2002 by CRC Press LLC
F REF
F REF
N
.
Phase
Detect
Phase
Detect
U
D
U
D
Charge
Pump
Charge
Pump
C
C
R
V CTRL
V CTRL
VCDL
VCO
F O
F O