U. Glaeser

FIGURE 11.8 Current-mode CMOS quaternary threshold logic full adder with feedback schematic.
comparators realized with simple Widlar current mirrors of four-micron channel lengths and greater
have been found to be adequate to resolve the eight-valued signals used in this circuit.
One potential problem with this QFA is the possible error accumulation involved with the analog
summing of seven logical currents at a node; the higher the logical value of the weighted-sum-of-inputs,
the greater error possible in the sum of currents. For increasing threshold current the current comparator
circuits exhibit decreasing gain, and therefore reduced ability to discriminate the threshold function. The
QFA has less accuracy in discriminating the presence of the higher valued weighted sums of inputs. To
compensate for this decreasing gain with increasing threshold currents, we examine a feedback technique
which eliminates the need to use the three largest values of threshold currents.
A schematic of one version of this QFA modified with feedback is shown in Fig. 11.8. In the figure we
see that a current of four logical units in value is combined with a copy of the weighted-sum-of-inputs
to create a new input current that is I in2 = (I in − 4) when the weighted sum of inputs exceeds logical four.
The same three lowest threshold current comparators with greatest gain can now be used to generate the
entire range of QFA SUM outputs. The QFA circuit with feedback operates as follows. The threshold
current for the “D” comparator that controls the CARRY output is generated by PMOS transistor M 3. The
input is first compared to this threshold to determine whether the input range is above or below 4. If the
input is below 4, the output D is in the HIGH state. D is inverted to drive a pair of transmission gates;
one controls the CARRY output current, the other controls the four units of logical current that are fed
into the drain of M 6. At the drain of M 6, this feedback current is summed with a copy of the input current
to form the total drain current of M 6. If the CARRY output is ZERO, no current is fed back and the M 6
drain current is equal to the input current. Let us assume for this discussion that the input current is, for
example, logical six. The input current will be mirrored by M 6 to generate a total drain current of logical
six. Since the D comparator has switched to turn on the CARRY output, the feedback current transmission
gate is also conducting the logical four feedback current into the node at the drain of M 6. The excess
current (logical six minus logical four = logical two) must be provided by transistor M 8. M 8 is a diode
connected PMOS transistor that serves as the input to the three current comparators that generate outputs
A, B, and C. These comparators operate exactly as described previously except that the roles of the PMOS
and NMOS transistors and thus the A, B, and C voltage swings have been reversed. The PMOS devices
M 9–M 11 serve as the input devices while the NMOS devices M 12–M 14 serve as the current reference devices.
This feedback technique eliminates the CMOS logic stage that encodes the comparator outputs into
controls signals for the transmission gates that then switch the logical current outputs onto the SUM
output line. The three largest current mirror transistors are also eliminated. The propagation delays
© 2002 by CRC Press LLC