U. Glaeser

1.2 Downsizing below 0.1
© 2002 by CRC Press LLC
µµµµ m
In digital circuit applications, a MOSFET functions as a switch. Thus, complete cut-off of leakage current
in the “off” state, and low resistance or high current drive in the “on” state are required. In addition,
small capacitances are required for the switch to rapidly turn on and off. When making the gate length
small, even in the “off” state, the space charge region near the drain—the high potential region near the
drain—touches the source in a deeper place where the gate bias cannot control the potential, resulting
in a leakage current from source to drain via the space charge region, as shown in Fig. 1.6. This is the
well-known, short-channel effect of MOSFETs. The short-channel effect is often measured as the threshold
voltage reduction of MOSFETs when it is not severe. In order for a MOSFET to work as a component
of an LSI, the capability of switching-off or the suppression of the short-channel effects is the first priority
in the designing of the MOSFETs. In other words, the suppression of the short-channel effects limits the
downsizing of MOSFETs.
In the “on” state, reduction of the gate length is desirable because it decreases the channel resistance
of MOSFETs. However, when the channel resistance becomes as small as source and drain resistance,
further improvement in the drain current or the MOSFET performance cannot be expected. Moreover,
in the short-channel MOSFET design, the source and drain resistance often tends to even increase in
order to suppress the short-channel effects. Thus, it is important to consider ways for reducing the total
resistance of MOSFETs with keeping the suppression of the short-channel effects. The capacitances of
MOSFETs usually decreases with the downsizing, but care should be taken when the fringing portion
is dominant or when impurity concentration of the substrate is large in the short-channel transistor
design.
Thus, the suppression of the short-channel effects, with the improvement of the total resistance and
capacitances, are required for the MOSFET downsizing. In other words, without the improvements of
the MOSFET performance, the downsizing becomes almost meaningless even if the short-channel effect
is completely suppressed.
To suppress the short-channel effects and thus to secure good switching-off characteristics of MOSFETs,
the scaling method was proposed by Dennard et al. [3], where the parameters of MOSFETs are shrunk
or increased by the same factor K, as shown in Figs. 1.7 and 1.8, resulting in the reduction of the space
charge region by the same factor K and suppression of the short-channel effects.
2
In the scaling method, drain current, Id
( = W/
L × V / tox),
is reduced to 1/
K.
Even the drain current is
reduced to 1/
K,
the propagation delay time of the circuit reduces to 1/
K,
because the gate charge reduces
2
to 1/
K . Thus, scaling is advantageous for high-speed operation of LSI circuits.
2
If the increase in the number of transistors is kept at K , the power consumption of the LSI—which
2
is calculated as 1/
2fnCV as shown in Fig. 1.7—stays constant and does not increase with the scaling.
Thus, in the ideal scaling, power increase will not occur.
FIGURE 1.6
Source
Leakage Current
0 V
Space Charge
Region
Short channel effect at downsizing.
0 V
Gate
V dd (V)
Drain