U. Glaeser

FIGURE B. Terms relating to data dependencies occurring in straight line code (Instruction semantics is r 1 ← r 2∗r 3
etc.).
arise in scenarios when an instruction uses a register operand, which needs to have been loaded by a
preceding load instruction from the memory, as shown in the example in Fig. B. If, however, the requested
operand is produced by a preceding operational instruction, the arising dependency is called define-use
dependency, as illustrated in Fig. B.
WAR dependencies or anti-dependencies arise between instructions if a given instruction reads an
operand from a particular register and a subsequent instruction writes the same register, as depicted in
Fig. B. If, for any reason, the subsequent instruction (i 2) would have written this register before it is read
by the previous one (i 1), then the subsequent instruction would pick up an erroneous operand value.
Finally, two instructions are said to be WAW dependent, or output dependent, if they both write the
same destination.
WAR and WAW dependencies are designated as false dependencies, since they can be removed by
appropriate techniques (that is register renaming in the case of register operands). By contrast, RAW
dependencies are true dependencies, since they cannot be eliminated.
Data dependencies may also occur in loops. This is the case if an instruction of the loop body is
dependent on an instruction belonging to a previous loop iteration, as exemplified in Fig. A. This type
of dependency is called recurrence, designated also as inter-iteration data dependency or loop carried
dependency. In the above example the value of X(I) depends on the value that is computed in the previous
iteration. The recurrence shown is a first-order linear one.
Appendix B: The Principle of Instruction Shelving
Instruction shelving (also known as indirect issue or dynamic instruction scheduling) 1–3,49 removes the
issue bottleneck caused by control and data dependencies and by busy execution units. Its main idea is
to “shelve” issued instructions and defer dependency checking until a subsequent processing step, designated
as dispatching.
Without shelving (see Fig. C) the processor issues instructions from the so called issue window (instruction
window), to the execution units (EU). Actually, the issue window comprises the last n entries of the
instruction buffer (I-buffer), where n is the issue rate. The processor decodes the instructions kept in the
window and checks for dependencies between the instructions in the window and those in execution,
and also among the instructions held in the window. Dependent instructions are not issued, moreover,
depending on the issue policy of the processor, 36 they can even block the issue of subsequent not
dependent instructions. Occurring blockages heavily restrict the average number of instructions issued
per cycle and thus also processor performance.
© 2002 by CRC Press LLC
Load-use
dependency
i1: load r1, var
i2: add r3, r1, r2
RAW
Read-after-Write
dependency
(Flow dependency)
Define-use
dependency
i1: mul r1, r2, r3
i2: add r5, r1, r4
True dependencies
Cannot be
abandoned
Inter-instruction
data dependencies
WAR
Write-after-Read
dependency
(Anti dependency)
i1: mul r1, r2, r3
i2: add r2, r4, r5
False dependencies
Can be eliminated
by register renaming
WAW
Write-after-Write
dependency
(Output dependency)
i1: mul r1, r2, r3
i2: add r1, r4, r5