U. Glaeser

FIGURE 1.15 NiSi Salicide [10].
FIGURE 1.16 ITRS’99. (a) CPU clock frequency, (b) gate length, (c) supply voltage, and (d) gate insulator thickness.
was no narrow line effect—increase in the sheet resistance in narrow silicide line—and bridging failure
by the formation of silicide path on the gate sidewall between the gate and S/D. NiSi-contact resistances
to both n + and p + Si are small. These properties are suitable for reducing the source, drain, and gate
resistance for sub-50 nm MOSFETs.
The previous discussion provides examples of possible solutions, which the authors found in the 1990s
for sub-50 nm gate length generation. Also, many solutions have been found by others. In any case, with
the possible solutions demonstrated for sub-50 nm generation as well as the keen competitions among
semiconductor chipmakers for high performance, the downsizing trend or roadmap has been significantly
accelerated since late 1990s, as shown in Fig. 1.16. The first roadmap for downsizing was published in
1994 by SIA (Semiconductor Industry Association, USA) as NTRS’94 (National Technology Roadmap for
Semiconductors) [11]—at that time, the roadmap was not an international version. On NTRS’94, the clock
frequency was expected to stay at 600 MHz in year 2001 and expected to exceed 1 GHz in 2007. However,
it has already reached 2.1 GHz for 2001 in ITRS 2000 [12]. In order to realize high clock frequencies, the
© 2002 by CRC Press LLC
CPU Clock Frequency (MHz)
10
(c)
V dd (V)
10 4
10 3
1
(a)
Intel
1994 Version
1999
2000 update
1994
1999
10 2
1990 1995 2000 2005 2010 2015
Year
0.1
1990 1995 2000 2005 2010 2015
Year
T ox equivalent (nm) L g ( m)
µ
1
(b)
0.1
2000 update
0.01
1990 1995 2000 2005 2010 2015
Year
10
(d)
5
3
1999
Intel
0.35
0.25
0.14
0.12
1994
0.18
1994
0.13
0.10 0.07
?
Direct
tunneling
limit
SiO 2
0.10 0.080 1999
1
0.070
0.065
?
Intel (2000) 0.045 0.022
0.032 High-k insulator?
0.5
1990 1995 2000 2005 2010 2015
Year