U. Glaeser

FIGURE 2.95 Low-voltage trends in digital circuits.
FIGURE 2.96 MTCMOS circuit scheme.
and shows the trend in power consumption per basic gate, normalized to the power consumption for
5 V operation. The supply voltage for 0.05 µm generation LSI circuits is predicted to be 0.5 V in the year
2011, a reduction of two orders of magnitude from the 5 V operation of the 0.5 µm generation. However,
it is possible to realize wearable information equipment that requires ultra-low-power-consumption
ahead of that low-voltage, low-power consumption time trend, even without waiting for the finer processes
of 2011, by using a combination of FD-SOI devices and MTCMOS circuits [24] or adiabatic
charging circuits [25]. NTT is proceeding along a low-voltage research roadmap that shows 1 V operation
in the year 2000 and 0.5 V operation sometime between 2003 and 2005.
MTCMOS (Multi-Threshold CMOS) circuits [24] are an effective means to achieve lower operating
voltages in digital circuits (Fig. 2.96). These circuits are constructed of MOSFETs that have two different
© 2002 by CRC Press LLC
1990 1995 2000 2005 2010
1
500 nm
350 nm
0.1
0.01
0.001
MTCMOS/bulk-Si
device
SL
Variable threshold
power-switch
Fully Depleted
Low-V th MOSFET
250 nm
180 nm
From 1999 SIA Roadmap
130 nm
100 nm
1.2 V
70 nm
20 MHz
1 V
50 nm
100 MHz
0.5 V
100 MHz
MTCMOS/0.18-
0.15- µ m FD-SOI
device
V DD = 0.5 V
Year
Adiabatic Charging
Circuit/ 0.1- µ m FD-SOI
device
Virtual V DD
Low-threshold
CMOS logic gaters
Partially Depleted
High-V th MOSFET