U. Glaeser

FIGURE 14.13 Domino AF reduction in a Mux.
FIGURE 14.14 Power/area/delay trade-offs for PLA vs. synthesized logic.
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DIN
FIGURE 14.15 Latch redesign example.
Another example of power/performance trade-off is in the case of control logic, which can either be
implemented in PLAs or synthesized gates. Figure 14.14 shows the results for a logic block whose seven
sub-blocks can be implemented in PLAs or as synthesized random logic. Increasing the number of
synthesized blocks leads to some increase in delay but with much larger power savings.
In library-based design, power savings from the design of the cell libraries can come from device sizing
and from restructuring of the logical and physical schematics of the cell. Again, device sizing for optimizing
switching energy versus delay ensures better power efficiency; however, resizing of the sequential
cells requires extensive recharacterization for setup and hold times in addition to delays of clock to data
output.
The second way to optimize a cell library is to change the schematics of the most commonly used and
most power hungry cells in the design. These typically consist of latches and master slave flip-flops since
these have clock nodes which switch on at every clock edge. Figure 14.15 shows an example of latch
redesign that gets rid of clock nodes while still maintaining functionality and performance. Thus, it is
advisable to replace more dissipative sequential cells by more efficient types. A small amount of redesign
effort on some selected cells often can have a significant power impact for the full chip.
© 2002 by CRC Press LLC
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(All synthesized)
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