U. Glaeser

FIGURE 21.26 Energy per cycle vs. frequency simulation results for all three processors (data combined from [28]
© 1997 IEEE and [29] © 2000 IEEE).
clock phases. For MD1, conventional buffers were used to drive the two clock phases. These buffers were
powered from a separate dc supply, so that clock power was recorded separately than the core power.
For both AC-1 and MD1, the operating power under resonant mode was projected by dividing the clock
power under conventional mode by 6.5. This factor indicates the efficiency of the all-resonant clock driver
and was derived from laboratory measurements.
The simulation results are shown in Fig. 21.26. For DC1, the operating frequency ranged from 20 MHz
at 1.5 V to 143 MHz at 3.3 V. Power dissipation ranged from 2.7 mW (at 20 MHz) to 100 mW (at
143 MHz). For AC-1, the top operating frequency was 74 MHz. For increasing frequency, clock voltage
ranged from 2.4 to 3.3 V and core voltage ranged from 1.8 to 2.6 V. As discussed earlier, the AC-1 logic
style requires that the clock voltage swing be a threshold voltage higher than the core voltage. Power
dissipation under conventional mode was 22.3 mW at 33.3 MHz and 95.1 mW at 74 MHz. The projected
power dissipation under resonant mode is 4.7 and 21.5 mW, respectively. For MD1, the top frequency
was 110 MHz. For all operating points, clock and core voltages were maintained at the same level ranging
from 1.4 V at 10 MHz to 2.7 V at 110 MHz. Power dissipation was 2.1 mW at 10 MHz and 108 mW at
110 MHz. The power dissipation in resonant mode would be 850 µW and 34 mW, respectively.
Simulation results show that MD1 is a more efficient design than AC-1 in terms of power dissipation
and operating frequency especially under conventional mode. The significantly higher power dissipation
of AC-1 under conventional mode is attributed to the higher clock voltage swing. Therefore, applying
energy recovery has a greater effect on AC-1 than on MD1 since clock power is a larger portion of the
total power for AC-1 when both processors operate in conventional mode. For MD1 under conventional
mode, the clock-powered nodes (including the two clock phases) account for 80% of the total power
dissipation. Clock-powered nodes are about 5% of the total nodes. Both AC-1 and MD1 would dissipate
less power than DC1 when they operate under resonant mode. Specifically, the projected MD1 dissipation
under resonant mode would be about 40% less than the dissipation of DC1.
21.8 Conclusions
In this chapter, clock-powered logic was discussed as a low-overhead, node-selective adiabatic style for
low-power CMOS computing. The merit of clock-powered logic is that it combines the low-overhead
of standard CMOS for driving low-capacitance nodes and the superior energy versus delay scalability
of adiabatic charging for high-capacitance nodes. All the components of a clock-powered microsystem
were presented in detail. Clock-powered logic is more effective for applications in which a small
percentage of nodes accounts for most of the dynamic power dissipation (e.g., processors, memory
structures [32], etc.).
© 2002 by CRC Press LLC
mW / MHz
1.2
1
0.8
0.6
0.4
0.2
0
0 50 100 150
Frequency (MHz)
AC 1 convent. dr.
MD1 convent. dr.
DC1
AC 1 resonant dr.
MD1 resonant dr.